Makefile Notes

Makefile Notes

1. Core Idea of Makefile

The structure of a typical makefile is as below:

target: dependency1 denpendency2...
	command
	.......

When we type make target in terminal, make will first examine whether the target exists and then examine whenter the revison date of all dependecies is not beyond target. If either of above examinations fails, the command will be executed.
If one of the dependencies doesn't exist, make look for the target which has the same name of that dependency and then try to execute corresponding commands.

2. Variables in Makefile

Variables in makefile are much like macros in C, except that the declaration of variables in makefile uses = or := rather than #define. The value of a variable is always a string. We can get the valuVe of a variable via $(varname).
If you want to make a varialbe global when you include other makefiles, use export ahead of variable name.
Use += to append a string to a variable.

3. Automatic Variables

A example:

all: target1 target2
target1 target2: dp1 dp2
	@echo $@
	@echo $^
	@echo $?

Result of make all:

Note that the result doesn't show the executed command, which will be printed by default, as a consequence of @ we put in front of command.

$@ represents the corresponding target name.
$^ represents all the dependencies.
$? represents all the dependencies which are newer than target.