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echo: 用于字符串的输出。命令格式: echo "It is a test" //可以省略双引号; 显示转义字符 echo "\"It is a test\"" //可以省略双引号; 变量 #!/bin/sh read name echo "$name It is a test" read是一个 阅读全文
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pip 列出所有安装的库 pip list 列出所有过期的库 pip list --outdated 安装pip-review。 pip install pip-review pip-review --local --interactive pip-review ERROR: Could not i 阅读全文
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81.A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal. D flip-flops are create 阅读全文
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知乎上有个详细的解答专栏:https://zhuanlan.zhihu.com/c_1131528588117385216 73.Implement the circuit described by the Karnaugh map below. module top_module( input a 阅读全文
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66.Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out. module top_module( input a, b, output cout, su 阅读全文
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61.Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b. module top_module( input a, b, sel, output out ); assign out 阅读全文
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44.Implement the following circuit: in-->out module top_module ( input in, output out); assign out=in; endmodule 45.Implement the following circuit: m 阅读全文
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[注]这个网站比较神奇的一点就在于,不解出来就不让你看答案。所以经常一个错误卡好久。。不过有大佬在GitHub发过答案了: https://github.com/M-HHH/HDLBits_Practice_verilog 31.Build a 2-to-1 mux that chooses bet 阅读全文
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16.Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, 阅读全文
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听别人推荐了一个Verilog刷题网站:https://hdlbits.01xz.net/wiki/Main_Page 01.Build a circuit with no inputs and one output. That output should always drive 1 (or lo 阅读全文
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Chapter07 用户输入和while 循环 input() age = input("How old are you? ") print(age) #默认为字符串 age = int(age) print(age) #强制类型转换 while current_number = 1 while c 阅读全文
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目的主要是提取下TFT的电学模型,应用于Hspice的仿真。基于level61或level62或者verilog-A编辑的模型。 2020.04.06 建个数据库: utmost4 user Manuel:2.2 Creating a Database On Windows, you can dou 阅读全文
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参考文献: (1)HSPICE® User Guide:Simulation and Analysis-Chapter29 Using Verilog-A (2)Verilog-AMS Language Reference ManualAnalog & Mixed-Signal Extensions 阅读全文