verilog | 时钟信号与复位信号

  1 //1.常规时钟
  2 
  3 //1) initial:
  4 
  5 parameter clk_period = 10;
  6 
  7 reg clk;
  8 
  9 initial begin
 10 
 11 clk = 1'b0;
 12 
 13 forever
 14 
 15 #(clk_period / 2) clk = ~clk;
 16 
 17 end
 18 
 19 
 20 
 21 //2) always:
 22 
 23 parameter clk_period = 10;
 24 
 25 reg clk;
 26 
 27 initial
 28 
 29 clk = 0;
 30 
 31 always #(clk_period / 2) clk = ~clk;
 32 
 33 
 34 
 35 //2.占空比可调时钟
 36 
 37 //占空比:High_time / (High_time + Low_time)
 38 
 39 parameter High_time = 5, Low_time = 10;
 40 
 41 reg = clk;
 42 
 43 always
 44 
 45 begin
 46 
 47 clk = 1;
 48 
 49 # High_time;
 50 
 51 clk = 0;
 52 
 53 # Low_time;
 54 
 55 end
 56 
 57 
 58 
 59 //3.偏移相位时钟信号
 60 
 61 //相位偏移:360 * pshift_time / (High_time + Low_time)
 62 
 63 parameter High_time = 5, Low_time = 10, pshift_time = 2 64 
 65 reg = clk;
 66 
 67 always
 68 
 69 begin
 70 
 71 clk = 1;
 72 
 73 # High_time;
 74 
 75 clk = 0;
 76 
 77 # Low_time;
 78 
 79 end
 80 
 81 assign #(pshift_time) clk_p = clk;
 82 
 83 
 84 
 85 //4.固定数目时钟信号
 86 
 87 parameter clk_cnt = 50, clk_period = 2;
 88 
 89 reg clk;
 90 
 91 initial
 92 
 93 begin
 94 
 95 clk = 0;
 96 
 97 repeat(clk_cnt)
 98 
 99 #(clk_period / 2) clk = ~clk;
100 
101 end
102 
103 
104 
105 //5.复位信号
106 
107 //1)异步复位
108 
109 parameter rst_repiod = 100;
110 
111 reg rst_n;
112 
113 initial
114 
115 begin
116 
117 rst_n = 0;
118 
119 #rst_repiod;
120 
121 rst_n = 1;
122 
123 end
124 
125 
126 
127 //2)同步复位
128 
129 parameter rst_repiod = 100;
130 
131 reg rst_n;
132 
133 initial begin
134 
135 rst_n = 1;
136 
137 @(posedge clk)
138 
139 rst_n = 0;
140 
141 #rst_repiod;
142 
143 rst_n = 1;
144 
145 end

 

posted on 2020-07-15 15:19  JiFengZ  阅读(432)  评论(0编辑  收藏  举报

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