摘要： 1 clock module top_module ( ); reg clk; dut U1(.clk(clk)); initial begin clk = 0; end always begin #5; clk = ~clk; end endmodule 2 Tb/tb1 module top_m 阅读全文

摘要： 1 Finding bugs in code 1.1 Bugs mux2 module top_module ( input sel, input [7:0] a, input [7:0] b, output [7:0] out ); assign out = sel ? a:b; endmodul 阅读全文