2020年4月8日
4 Data Structures
摘要： 4 Data StructuresThis section describes data structures used by NVM Express.4.1 Submission Queue & Completion Queue DefinitionSections 4.1, 4.1.1 and 阅读全文
posted @ 2020-04-08 19:51 话说吴语 阅读(686) 评论(0) 推荐(0)
3 Controller Registers
摘要： Controller registers are located in the MLBAR/MUBAR registers (PCI BAR0 and BAR1) that shall be mapped to a memory space that supports in-order access 阅读全文
posted @ 2020-04-08 19:43 话说吴语 阅读(473) 评论(0) 推荐(0)
2.6 Advanced Error Reporting Capability (Optional)
摘要： 2.6 Advanced Error Reporting Capability (Optional)The Advanced Error Reporting definitions below are based on the PCI Express 2.1 Base specification. 阅读全文
posted @ 2020-04-08 16:01 话说吴语 阅读(2618) 评论(0) 推荐(0)
2.5 PCI Express Capability
摘要： The PCI Express Capability definitions below are based on the PCI Express 2.1 Base specification. Implementations may choose to base the device on a s 阅读全文
posted @ 2020-04-08 15:52 话说吴语 阅读(1401) 评论(0) 推荐(0)
2.2 PCI Power Management Capabilities
摘要： Note: It is recommended that the controller allocate a unique MSI-X vector for each Completion Queue.The Table BIR and PBA BIR data structures may be 阅读全文
posted @ 2020-04-08 15:45 话说吴语 阅读(751) 评论(0) 推荐(0)