2020年3月30日
2.1 PCI Header
摘要： NOTE: NVM Express implementations that reside behind PCI compliant bridges, such as PCI Express Endpoints, are restricted to having 32-bit assigned ba 阅读全文
posted @ 2020-03-30 20:28 话说吴语 阅读(1027) 评论(0) 推荐(0)
2 System Bus (PCI Express) Registers
摘要： This section describes the PCI Express register values when the PCI Express is the system bus used. Other system buses may be used in an implementatio 阅读全文
posted @ 2020-03-30 20:19 话说吴语 阅读(568) 评论(0) 推荐(0)
1 Introduction（一）
摘要： 1 Introduction1.1 OverviewNVM Express (NVMe) is an interface that allows host software to communicate with a non-volatile memory subsystem. This inter 阅读全文
posted @ 2020-03-30 19:53 话说吴语 阅读(985) 评论(0) 推荐(0)