CMOS Circuit Design Layout and Simulation

到 https://www.bookzz.ren/ 下了些书，按size从大到小排序，翻完即删，反正也看不懂啊。翻指的是查找字符串simulat，下错书了 :-)

这本书是Winner of The Frederic Emmons Terman Award in Electrical & Computer Engineering, 作者是R. Jacob Baker.

What's new in the third edition of CMOS? The information discussing computeraided design (CAD) tools (e.g., Cadence, Electric, HSPICE, LASI, LTspice, and WinSpice) has been moved to the book's webpage, http://CMOSedu.com.

The assumed background of the reader is a knowledge of linear circuits (e.g., RC and RLC circuits, Bode plots, Laplace transforms, AC analysis, etc.), microelectronics (e.g., diodes, transistors, small-signal analysis, amplifiers, switching behavior, etc.), and digital logic design.

To ensure the most practical computer validation of the designs, the simulations for the nanometer designs (a 50 nm process) use the BSIM4 SPICE models. Again, all of the book's simulation examples are available at CMOSedu.com.

SPICE: simulation program with integrated circuit emphasis.

We can use, among others, the Window's notepad or wordpad programs to create a SPICE netlist. SPICE likes to see files with "*.cir, *.sp, or *.spi" (among others) extensions.

The first SPICE simulation analysis we'll look at is the .op or operating point analysis. An operating point simulation's output data is not graphical but rather simply a list of node voltages, loop currents, and, when active elements are used, small-signal AC parameters. Consider the schematic seen in Fig. 1.10. The SPICE netlist used to simulate this circuit may look like the following (again, remember, that all of these simulation examples are available for download at CMOSedu.com):

Running the simulation gives the following output:

v(1) = 1.000000e+00
v(2) = 6.666667e-01
vin#branch = -3.33333e-04

The transfer function analysis can be used to find the DC input and output resistances of a circuit as well as the DC transfer characteristics. To give an example, let's replace, in the netlist seen above, .op with

.TF V(Vout,0) Vin

The form of the transient analysis statement is .tran tstep tstop <tstart> <tmax> <uic>

The netlist used to simulate the AC response of the circuit in Fig. 1.21 follows.

*#destroy all 
*#run 
*#plot db(vout/vin) 
*#set units=degrees 
*#plot ph(vout/vin) 
.ac dec 1001 10k 
Vin Vin 0 DC 0 SIN 0 1 200 AC 1 
R1 Vin Vout 1k 
CL Vout 0 1u 
.end

The SPICE pulse statement is used in transient simulations to specify pulses or clock signals. This statement has a format given by: pulse vinit vfinal td tr tf pw per

A switch can be simulated in SPICE using the following (for example) syntax:
s1 nodel node2 controlp controlm switmod
.model switmod sw ron=1k

Layout of the three-input minimum-size NOR and NAND gates is shown in Fig. 12.6, using the standard-cell frame.

 

The number of MOSFETs on a chip, depending on the application, can range from tens (an op-amp) to more than hundreds of millions (a 256 Mbit DRAM). VLSI designs can be implemented using many different techniques including gate-arrays, standard-cells, and full-custom design.

The steps involved in rendering a schematic diagram into its physical layout are plan, place, connect, polish, and verify. Polish... After your layout is basically finished, it is time to step back and take a look at it from a purely aesthetic point of view. Is it pleasing to the eye? Is the hook-up as straightforward as possible, or is it "busy" and hard to follow? Are the spaces between poly gates and contacts minimum? What about the space between diffusions? Are there enough contacts? Did you share all of the source and drain implants that can be shared? Are there sufficient well and substrate ties? If you have planned well and followed the plan described here, you shouldn't run into too many problems. [这段话都是?]

The number of rows in a DRAM is limited because each additional row adds capacitance to the bit line.

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