每个写Verilog的都应该懂点仿真器

0. Java面试高端局都要问虚拟机的, Java虚拟机，不是KVM和Xen.

1. 我一个外行老头子，都会那么一丢丢:

module m(input a, b, c);
reg y;
always @(a) begin $display("@(a)"); y=a; end
always @(a,b) begin $display("@(a,b)"); y=a&b; end
always @(a,b,c) begin $display("@(a,b,c)"); y=a&b&c; end
endmodule
module test;
reg a,b,c;
initial begin
a=1; #1 b=1; #1 c=1;
end
m m(a,b,c);
endmodule
@(a)
@(a,b)
@(a,b,c)
@(a,b)
@(a,b,c)
@(a,b,c)

幸好没有急急忙忙地去写toy simulator，不然不知道bug在哪里。好像看到过"只能/建议一个always块"? 还是initial? 例子中的always块是自找麻烦; Verilog有没有方法规定执行顺序?

Kernel-based Virtual Machine (KVM) is an open source virtualization technology built into Linux. 

Xen is a hypervisor that supports x86, x86_64, Itanium, and ARM architectures, and can run Linux, Windows, Solaris, and some of the BSDs as guests on their supported CPU architectures. It’s supported by a number of companies, primarily by Citrix, but also used by Oracle for Oracle VM, and by others.