抛砖引砖之大话Verilog里的level

我刚学Verilog，说的自然是砖。说得可能不中听，会引来板砖，所以很机智地没有开放评论。请看代码和注释：

// User Defined Primitives
primitive xor_cell_level(output c, input a, input b);
table    // truth table
//a b   c    
    1 1 : 0;
    0 1 : 1;
    1 0 : 1;
    0 0 : 0;
endtable
endprimitive

// Switch level is the lowest level of abstraction provided by Verilog.
// A module can be implemented in terms of transistors, switches, storage nodes,
// and the interconnections between them. 不太像人话啊——Sorry 我孤陋寡闻了，真可以写cmos, tran等

module xor_gate_level(output c, input a, input b); // Gate/Structural level
// a xor b = (a nand (a nand b)) nand (b nand (a nand b))
wire    ab, aab, bab;
nand    g1(ab, a, b), g2(aab, a, ab), g3(bab, b, ab), g4(c, aab, bab);
endmodule

module xor_data_flow_level(output c, input a, input b);
assign c = a ^ b;
endmodule

// Resister transfer Level (RTL) is the the MOST commonly used, and is NOT always synthesizable.
module test;
integer     a;
reg[1:0]    b;
wire c1, c2, c3, c4;
initial begin
    for(a = 0; a <= 1; a++)
        for(b = 0; b <= 1; b++)
            #1 $monitor("a=%b b=%b c1=%b c2=%b c3=%d c4=%d", a[0], b[0], c1, c2, c3, c4);
    #1 $finish;
end
xor_cell_level t1(c1, a[0], b[0]);
xor_gate_level t2(c2, a[0], b[0]);
xor    t3(c3, a[0], b[0]);
xor_data_flow_level    t4(c4, a[0], b[0]);
endmodule

// Verilog also supports behavioral/algorithmic level of abstraction with no regard to
// the structural realization of the design, which is primarily used for verification.
// It is the highest level of abstraction.
// behavioral: algorithms, flowcharts, state transition diagrams, RTL etc

Level? OSI还七层模型呢，大家用的不还是TCP/IP? 搞硬件的说coding style. 用不用类(class)是方法论的差异，不是coding style不同.

一本好书, I mean it, "Computer Architecture Tutorial Using an FPGA ARM"里出现了Verilog Codling sytle，不知他的意思是coding + modeling呢，还是typo.

Linux kernel coding style

iverilog不用带-o，默认生成a.out，里面有个shebang: #! /c/Source/iverilog-install/bin/vvp, Windows下不好使，得自己vvp a.out, Linux下就像是执行a.out一样。vvp带调试功能: Ctrl+C出来>提示符，finish退出，有些简单的调试命令，输入help可知。Apparently我曾经陷入死循环: b用了1个bit.

不加#1的话出不来四种组合:

***** 1.out
    %jmp/0xz T_0.3, 5;
    %vpi_call 2 34 "$monitor", "a=%b b=%b c1=%b c2=%b c3=%d c4=%d", &PV<v0000022484dd2790_0, 0, 1>, &PV<v0000022484dd2c90_0, 0,
 1>, v0000022484dd2010_0, v0000022484dd28d0_0, v0000022484dd1ed0_0, v0000022484dd2510_0 {0 0 0};
    ; show_stmt_assign_vector: Get l-value for compressed += operand
    %load/vec4 v0000022484dd2c90_0;
    %pushi/vec4 1, 0, 2;
***** A.OUT
    %jmp/0xz T_0.3, 5;
    %delay 1, 0;
    %vpi_call 2 34 "$monitor", "a=%b b=%b c1=%b c2=%b c3=%d c4=%d", &PV<v0000027e5441fba0_0, 0, 1>, &PV<v0000027e5441fc40_0, 0,
 1>, v0000027e544203c0_0, v0000027e5441fd80_0, v0000027e54420460_0, v0000027e5441fe20_0 {0 0 0};
    ; show_stmt_assign_vector: Get l-value for compressed += operand
    %load/vec4 v0000027e5441fc40_0;
    %pushi/vec4 1, 0, 2;
*****

* %delay <low>, <high>

This opcode pauses the thread, and causes it to be rescheduled for a time in the future. The amount is the number of the ticks in the future to reschedule, and is >= 0. If the %delay is zero, then the thread yields the processor for another thread, but will be resumed in the current time step. The delay amount is given as 2 32bit numbers, so that 64bit times may be represented. 从代码来看它好像并没有pthread_create，而是用单线程来模拟的——像协程。似乎未能充分利用多核CPU。