推荐的并行执行语句Case的编码风格

先看例子：

module  regwrite(

       output  reg  rout;

       input           clk;

       input [3:0]   in;

       input [3:0]   ctrl;  );

    always @ (posedge clk)

       begin

          rout <= 1’b0;      //这是亮点

          case(1)

              ctrl[0] : rout <= in[0];

              ctrl[1] : rout <= in[1];

              ctrl[2] : rout <= in[2];

              ctrl[3] : rout <= in[3];

          endcase

       end

endmodule

亦即在Case之前增加对输出的赋值。To ensure a value is always assigned to the register, an initial assignment can be used to assign a value to the register prior to the case statement. This type of coding style eliminates the need for a default case and also ensures that the register is assigned to the default value if no other assignment is defined.

整个思路的推导过程如下：if..else有优先级=>Case(1)有优先级=>加SynthesisDirective在仿真与综合时效果不一致=>加Default有Latch=>在Case之前赋初值