摘要:
--等占空比5分频电路 --div_5.vhd file LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY div_5 IS PORT(clk_in:IN std_logic; clk_out:OUT std_logic );END div_5; ARCHITECTURE rtl OF div_5 IS SIGNAL clk_up,clk_down:s... 阅读全文
posted @ 2012-04-18 12:33
风波邪人
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