摘要: module bbbb(clock,oo,ii);input clock;output [4:0]oo;output [4:0]ii;reg [4:0]ooo;reg [4:0]iii;always@(posedge clock)begin if(ooo>=16) begin ... 阅读全文
posted @ 2015-12-27 23:34 Deja 阅读(2738) 评论(0) 推荐(0)