(转)UVM挑战及概述
UVM的调度也具有其独特的挑战,尤其是在调试的领域。其中的一些挑战如下：
1. Phase的管理：objections and synchronization
2. 线程调试
3. Tracing issues through automatically generated code, macro expansion, and parameterized classes
4. 默认的错误信息详细但是难以捉摸
5. 扩展带有方法的类里面有些隐式的功能也许是不期望的
6. 对象ID跟对象句柄不同
7. 可视化动态类型和短暂的类
Debugging even simple issues can be an arduous task without UVM-aware tools. Here is a public webinar that reviews how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.
uvm一些概念：
1. uvm_top是在uvm_pkg里面的静态类变量用于保存uvm_root的handle。你应该永远不要用这个变量，uvm_test_top是顶级实例名。
根据功能，UVM类库里面包含：
1. Globals：在uvm_pkg的scope里面定义了很多类型，变量，function，和task，通过import uvm_pkg，来访问这些scope。
2. Base和组件：用于搭建testbench的基本组件，包含两类：component和object：
1. component用于搭建整个testbench的骨架，下面是一些
2. objec则是在不同组件之间进行流动的动态数据，下图是一些功能函数。
uvm_transaction：Using the field automation concept of uvm, all the above defines methods can be defined automatically.
3. Reporting：报告类提供一个工具来发布报告(消息)一致的格式和可配置的，比如日志记录到一个文件或退出仿真，users可以使用verbosity，unique ID或者severity过滤报告
uvm_report_object提供了到UVM reporting facility的接口：
1. ID--a unique id to form a group of messages.这个ID怎么依照怎样的关系进行分配，怎样进行有效的组织
2. message：
3. Verbosity：表示其相对重要性
4. filename/line：可以重写，对filename 进行预处理。
Following are the actions defined:
UVM_NO_ACTION -- Do nothing
UVM_DISPLAY -- Display report to standard output
UVM_LOG -- Write to a file
UVM_COUNT -- Count up to a max_quit_count value before exiting
UVM_EXIT -- Terminates simulation immediately
UVM_CALL_HOOK -- Callback the hook method .
4. Factory：用于生产制造UVM的对象和组件。使用工厂允许动态可配置组件层次结构和对象替换而不需要修改他们的代码,并在不破坏封装，用于对象替换
5. Phasing：用于管理仿真流程：
1. virtual function void build():构造不同子组件的components/ports/exports以及做对应的配置
2. virtual function void connect： used for connecting the ports/exports of the components.
3. virtual function void end_of_elaboration()：用于在需要的时候配置组件
4. virtual function void start_of_simulation() ：打印banners和topology
5. virtual task run()：test的主体
6. virtual function void extract()：收集需要的信息
7. virtual function void check()：进行检查
8. virtual function void report()：报告pass、fail状态
1. 只有build和final的方法是自顶向下执行，只有run方法是消耗时间的：
2. 注意build方法里面super.build的位置
6. Policy类： printing, comparing, recording, packing, and unpacking of uvm_object based classes.用于对这些功能提供具体的实现，可以被重写
7. TLM类，事务级接口
The advantages of TLM interfaces are
1) Higher level abstraction
2) Reusable. Plug and play connections.
3) Maintainability
4) Less code.
5) Easy to implement.
6) Faster simulation.
7) Connect to Systemc.
8) Can be used for reference model development.
Operation Supported By Tlm Interface:
Putting: Producer transfers a value to Consumer.
Getting: Consumer requires a data value from producer.
Peeking: Copies data from a producer without consuming the data.
Broadcasting: Transaction is broadcasted to none or one or multiple consumers.
Tlm Terminology :
Producer: A component which generates a transaction.
Consumer: A component which consumes the transaction.
Initiator: A component which initiates process.
Target: A component which responded to initiator.
TLM Interface Compilation Models:
Blocking:
A blocking interface conveys transactions in blocking fashion; its methods do not return until the transaction has been successfully sent or retrieved. Its methods are defined as tasks.
Non-blocking:
A non-blocking interface attempts to convey a transaction without consuming simulation time. Its methods are declared as functions. Because delivery may fail (e.g. the target component is busy and can not accept the request), the methods may return with failed status.
Combined:
A combination interface contains both the blocking and non-blocking variants.
Direction:
Unidirectional: Data transfer is done in a single direction and flow of control is in either or both direction.
Bidirectional: Data transfer is done in both directions and flow of control is in either or both directions.
8. Configuration and resources：提供一个配置数据库，配置数据库用于存储和检索配置时间和运行时属性, 这种机制只能对component使用，
string inst_name: Hierarchical string path.
string field_name: Name of the field in the table.
bitstream_t value: In set_config_int, a integral value that can be anything from 1 bit to 4096 bits.
bit clone : If this bit is set then object is cloned.
inst_name and field_name are strings of hierarchal path. They can include wile card "*" and "?" characters. These methods must be called in build phase of the component.
"*" matches zero or more characters
"?" matches exactly one character
There are two ways to get the configuration data:
1)Automatic : Using Field macros
2)Manual : using get_config_* methods
9. Sychronization：UVM提供同步类过程同步事件和barrier
10 sequencer and sequence：用于产生激励
1. sequence是一系列的事务，用户可以定义复杂的激励，sequence可以重用，扩展，随机，通过并行和串行方式组成更加复杂的sequence
2. 使用uvm_sequence的好处：
Sequences can be reused.
Stimulus generation is independent of testbench.
Easy to control the generation of transaction.
Sequences can be combined sequentially and hierarchically.
一个完整的sequence产生需要4种类：
1- Sequence item.
2- Sequence
3- Sequencer（负责sequence和driver之间的协调，并行运行多个序列，sequencer负责在两个序列之间进行仲裁，有两种sequencer：uvm_sequencer and uvm_push_sequencer）
4- Driver： initiate requests for new transactions and drives it to lower level components. There are two types of drivers: uvm_driver and uvm_push_driver.
1. 当仿真进行到某个run time phase的时候，UVM会检查在这个phase里面有没有被set一个default sequence，如果有的话，就调用对应sequence的body（）。
2. 当body的方法被调用的时候，使用create方法创建一个事务
3. 当事务创建好了之后，会调用wait_for_grant()，这是一个blocking的方法
4. 当driver的run task，当调用seq_item_port.get_next_item()的时候，sequencer会 un blocks wait_for_grant()方法
如果sequencer有多个sequence需要执行，则基于仲裁策略，un blocks 这个wait_for_grant()方法
5. After the wait_for_grant() un blocks, then transaction can be randomized, or its properties can be filled directly. Then using the send_request() method, send the transaction to the driver.
6. After calling the send_request() method, "wait_for_item_done()" method is called. This is a blocking method and execution gets blocks at this method call.
7. driver将这个transation发送到BUS
8. Once the driver operations are completed, then by calling "seq_item_port.put(rsp)", wait_for_item_done() method of sequence gest unblocked. Using get_responce(res), the response transaction from driver is taken by sequence and processes it.
pull和push：
Pull mode means, driver pulls the transaction from the sequencer when it requires.
uvm driver has 2 TLM ports.
1) Seq_item_port: To get a item from sequencer, driver uses this port. Driver can also send response back using this port.
2) Rsp_port : This can also be used to send response back to sequencer.
三类预定义的sequences：
1)uvm_random_sequence：从sequencer sequence的库里面随机的选择执行一个sequence包括uvm_random_sequence自己，uvm_exhaustive_sequence，
2)uvm_exhaustive_sequence：随机的选择执行每个sequence一次，除了自己和random sequence
3)uvm_simple_sequence
sequencer queue
从sequence id 2到最后的sequence，所有的sequence都是随机执行。如果sequencer里面的count变量被设置成0.那么没有sequence会执行，如果count变量设置成-1，then some random number of sequences from 0 to "max_random_count" are executed. By default "max_random_count" is set to 10. "Count" and "max_random_count" can be changed using set_config_int().
默认情况下，default_sequence是uvm_random_sequence
Body Callbacks：uvm sequences有两种callback方法，pre_body和post_body()： These callbacks are called only when start_sequence() of sequencer or start() method of the sequence is called.
Hierarchical sequences：To create a sequence using another sequence, following steps has to be done
1)Extend the uvm_sequence class and define a new class.
2)Declare instances of child sequences which will be used to create new sequence.
3)Start the child sequence using <instance>.start() method in body() method.
sequencer仲裁：When all the parallel sequences are waiting for a grant from sequencer using wait_for_grant() method, then the sequencer, using the arbitration mechanism, sequencer grants to one of the sequencer.
6种仲裁算法：
使用set_arbitation()方法设定仲裁算法
Sequence Registration Macros does the following
1) Implements get_type_name method.
2) Implements create() method.
3) Registers with the factory.
4) Implements the static get_type() method.
5) Implements the virtual get_object_type() method.
6) Registers the sequence type with the sequencer type.
7) Defines p_sequencer variable. p_sequencer is a handle to its sequencer.
8) Implements m_set_p_sequencer() method.
Exclusive Access：There are 2 mechanisms to get exclusive access:
Lock-unlcok
Grab-ungrab
11. Macros：简化复杂的实现
12. Containers：参数化的数据结构，提供queue和pool服务，The class based queue and pool types allow for efficient sharing of the datastructures compared with their SystemVerilog built-in counterparts.
13. command line processor：用于命令行的处理
如果代理是活跃的,子类型应该包含三个子组件。如果代理是被动的,子类型应该只包含监控。
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