07 2017 档案

HDL代码风格建议（2）乘法器和DSP推断
摘要：Inferring Multipliers and DSP Functions Inferring Multipliers module unsigned_mult (out, a, b); output [15:0] out; input [7:0] a; input [7:0] b; assig 阅读全文
posted @ 2017-07-20 10:26 大雪球 阅读(288) 评论(0) 推荐(0)
HDL代码风格建议（1）使用示例和IP
摘要：Recommended HDL Coding Styles HDL coding styles can have a significant effect on the quality of results that you achieve for programmable logic design 阅读全文
posted @ 2017-07-20 09:31 大雪球 阅读(246) 评论(0) 推荐(0)
推荐 的FPGA设计经验（4） 时钟和寄存器控制架构特性使用
摘要：Use Clock and Register-Control Architectural Features FPGAs provide device-wide clocks and register control signals that can improve performance. Use 阅读全文
posted @ 2017-07-20 01:09 大雪球 阅读(717) 评论(0) 推荐(0)
推荐 的FPGA设计经验（3） 物理实现和时间闭环优化
摘要：Optimizing Physical Implementation and Timing Closure Planning Physical Implementation When planning a design, consider the following elements of phys 阅读全文
posted @ 2017-07-19 22:28 大雪球 阅读(496) 评论(0) 推荐(0)
推荐 的FPGA设计经验（2）-时钟策略优化
摘要：Optimizing Clocking Schemes Avoid using internally generated clocks (other than PLLs) wherever possible because they can cause functional and timing p 阅读全文
posted @ 2017-07-19 17:55 大雪球 阅读(754) 评论(0) 推荐(0)
推荐 的FPGA设计经验（1）组合逻辑优化
摘要：主要内容摘自Quartus prime Recommended Design Practices For optimal performance, reliability, and faster time-to-market when designing with Altera devices, y 阅读全文
posted @ 2017-07-19 16:50 大雪球 阅读(1041) 评论(0) 推荐(0)
Quartus II 项目文件分类及内容
摘要：Quartus II 软件的项目文件后缀及其内容 阅读全文
posted @ 2017-07-19 10:49 大雪球 阅读(470) 评论(0) 推荐(0)