clk为什么要用posedge,而不用negedge
摘要:
Verilog中典型的counter逻辑是这样的:always@(posedge clk or negedge reset) begin if(reset == 1'b0) reg_inst1 <= 8'd0; else if(clk == 1'b1) reg_inst1 <= reg_inst1 + 1'd1; else reg_ins... 阅读全文
posted @ 2012-03-07 16:20 宕夏 阅读(13423) 评论(1) 推荐(2) 编辑