DC_Time and Load Budgeting

you should be able to:

    1、create a timing budget for a design block

    2、use the set_max_capacitance command to limit the input capacitance of a block

    3、budget the load on the output ports using the set_load command 

Timing budget:

#a generic time budgeting script file

         #for MY_BLOCK

create_clock -period 10 [get_parts clk]

set_dont_touch_network [get_clocks clk]

set_input_delay -max 6 -clock clk [all_inputs]

remove_input_delay [get_ports clk]

set_output_delay -max 6 -clock clk [all_outputs]

Load Budgeting:

    规格范例：

                1、任意模块的输入端口驱动最多只能放10个二输入与门

                2、任意模块的输出端口驱动最多只能接三个模块。

                current_design myblock

                link

                source timing_budget.tcl

#Assume a weak driving buffer on the inputs

set_driving_cell -lib_cell invla0 [all_inputs]

remove_driving_cell [get_ports clk]

#Limit the input load

set MAX_INPUT_LOAD [expr [load_of tech_lib/and2a0/A]*10]

set_max_capacitance $MAX_INPUT_LOAD [all_inputs]

remove_attribute [get_ports clk] max_capacitance

# Model the max possible load on the outputs,assuming

# outputs will only be tied to 3 subsequent blocks

set_load[expr $MAX_INPUT_LOAD*3] [all_outputs]

创建一个能应用到大型ASIC的子模块的默认脚本文件。

reset_design\

#Timing

create_clock -period 8 -name sysclk find(port,clk)

set_dont_touch_network find(clock,sysclk)

set_input_delay 4.8 -max -clock sysclk all_inputs() -find(port,clk)

set_output_delay 4.8 -max -clock sysclk all_outputs()

#Environment

set_operating_conditions -max ox_85_16

set_wire_load 40KGATES

set_driving_cell -cell invla0 all_inputs() -find(port,clk)

set_load load_of(cba_core/invla0/A)*40 all_outputs()

set_max_capacitance load_of(cba_core/invla0/A)*10

all_inputs()-find(port,clk)

约束描述的总结：

Timing and Area Goals:

set_max_area;create_clock;set_input_delay;

set_output_delay;set_dont_touch_network

Environmental Attributes:

set_driving_cell;set_load;set_operating_conditions;set_wire_load_model;

Design Rules:

set_max_capacitance

Reports:

report_clock;

report_port -verbose

report_design

write_scripts

Problems?

reset_design

remove_design

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