摘要：
DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a ... 阅读全文
posted @ 2014-08-15 15:54
CoryXie
阅读(3143)
评论(0)
推荐(0)
浙公网安备 33010602011771号