Computer Architecture - 随笔分类(第3页) - CoryXie

Multi-core compute cache coherency with a release consistency memory ordering model

摘要：A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first progr... 阅读全文

posted @ 2014-09-05 17:36 CoryXie

供多处理器系统中的高速缓存同步中使用的转发状态

摘要：这里所述的是一种具有五种状态的高速缓存同步协议，该五种状态为：修改、排它、共享、无效和转发(MESIF)。所述MESIF高速缓存同步协议包括转发(F)状态，该状态指明单个数据副本，从所述数据副本中能够产生另一个副本。利用F状态下的超高速缓冲存储器行来响应对超高速缓冲存储器行的副本的请求。在一个实施例中，将新创建的副本置于F状态下并将先前处于F状态下的超高速缓冲存储器行置成共享(S)状态或无效(I)... 阅读全文

posted @ 2014-09-05 09:39 CoryXie

供多处理器系统中的高速缓存同步中使用的转发状态

摘要：这里所述的是一种具有五种状态的高速缓存同步协议，该五种状态为：修改、排它、共享、无效和转发(MESIF)。所述MESIF高速缓存同步协议包括转发(F)状态，该状态指明单个数据副本，从所述数据副本中能够产生另一个副本。利用F状态下的超高速缓冲存储器行来响应对超高速缓冲存储器行的副本的请求。在一个实施例中，将新创建的副本置于F状态下并将先前处于F状态下的超高速缓冲存储器行置成共享(S)状态或无效(I)... 阅读全文

posted @ 2014-09-04 22:49 CoryXie

Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode

摘要：A processor supports an operating mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits... 阅读全文

posted @ 2014-09-03 00:55 CoryXie

Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes

摘要：A microprocessor contains an address generation unit, including a segment block, for loadingdescriptordata and a segment selector in a segment register. Twodescriptorloads from aglobaldescriptor... 阅读全文

posted @ 2014-09-02 23:26 CoryXie

Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system

摘要：A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual ma... 阅读全文

posted @ 2014-09-02 09:40 CoryXie

Methods and systems to control virtual machines

摘要：Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a process... 阅读全文

posted @ 2014-08-29 23:52 CoryXie

Power control within a coherent multi-processing system

摘要：Within a multi-processing system including a plurality of processor cores4, 6operating in accordance with coherent multi-processing, each of the cores includes a cache memory10, 12storing local cop... 阅读全文

posted @ 2014-08-21 10:51 CoryXie

Massively parallel supercomputer

摘要：A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Spec... 阅读全文

posted @ 2014-08-07 14:37 CoryXie

Distributed Symmetric Multiprocessing Computing Architecture

摘要：Example embodiments of the present invention includes systems and methods for implementing a scalable symmetric multiprocessing (shared memory) computer architecture using a network of homogeneous mul... 阅读全文

posted @ 2014-08-07 14:12 CoryXie

Method for performing cache coherency in a computer system

摘要：In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set... 阅读全文

posted @ 2014-08-07 14:03 CoryXie

Optimizing concurrent accesses in a directory-based coherency protocol

摘要：In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, ... 阅读全文

posted @ 2014-08-06 23:57 CoryXie

Store-exclusive instruction conflict resolution

摘要：A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20). Moni... 阅读全文

posted @ 2014-08-05 12:30 CoryXie

Next Instruction Access Intent Instruction

摘要：Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of... 阅读全文

posted @ 2014-08-04 23:06 CoryXie

Exclusive access control to a processing resource

摘要：A data processing system is provided with multiple processors that share a main memory. Semaphore values associated with data elements within the memory system, including the main memory, are used to ... 阅读全文

posted @ 2014-08-04 18:41 CoryXie

Methods and Systems for Enhancing Hardware Transactions Using Hardware Transactions in Software Slow-Path

摘要：Hybrid transaction memory systems and accompanying methods. A transaction to be executed is received, and an initial attempt is made to execute the transaction in a hardware path. Upon a failure to su... 阅读全文

posted @ 2014-07-31 00:02 CoryXie

Multi-processor having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactions

摘要：Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, ... 阅读全文

posted @ 2014-07-30 23:18 CoryXie

Efficient store queue architecture

摘要：One embodiment of the present invention provides a store queue that applies the stores to a memory subsystem in program order. This store queue includes a content-addressable memory (CAM), which holds... 阅读全文

posted @ 2014-07-30 12:30 CoryXie

Cache memory power reduction techniques

摘要：Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way... 阅读全文

posted @ 2014-07-30 00:41 CoryXie

Cache coherence protocol

摘要：A cache coherence protocol facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node. FIELD The invention relates to high-speed point-to-... 阅读全文

posted @ 2014-07-30 00:33 CoryXie

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随笔分类 - Computer Architecture