Computer Architecture - 随笔分类(第2页) - CoryXie

Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction

摘要：A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor amon... 阅读全文

posted @ 2014-09-23 21:52 CoryXie

Operating system management of address-translation-related data structures and hardware lookasides

摘要：An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page... 阅读全文

posted @ 2014-09-23 21:30 CoryXie

Memory Ordering in Modern Microprocessors

摘要：Linux has supported a large number of SMP systems based on a variety of CPUs since the 2.0 kernel. Linux has done an excellent job of abstracting away differences among these CPUs, even in kernel c... 阅读全文

posted @ 2014-09-22 23:46 CoryXie

Partitioned Replacement for Cache Memory

摘要：In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cach... 阅读全文

posted @ 2014-09-22 23:16 CoryXie

Multiprocessing system employing pending tags to maintain cache coherence

摘要：A pending tag system and method to maintain data coherence in a processing node during pending transactions in a transaction pipeline. A pending tag storage unit may be coupled to a cache controller a... 阅读全文

posted @ 2014-09-22 16:44 CoryXie

Extended symmetrical multiprocessor architecture

摘要：An architecture for an extended multiprocessor (XMP) computer system is provided. The XMP computer system includes multiple SMP nodes. Each SMP node includes an XMP interface and a repeater structure ... 阅读全文

posted @ 2014-09-22 16:34 CoryXie

Non-inclusive cache method using pipelined snoop bus

摘要：A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of the on-chip caches including data which i... 阅读全文

posted @ 2014-09-22 13:18 CoryXie

Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system

摘要：A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-system... 阅读全文

posted @ 2014-09-22 00:00 CoryXie

A multiprocessing system including an apparatus for optimizing spin-lock operations

摘要：A multiprocessing system having a plurality of processing nodes interconnected by an interconnect network. To optimize performance during spin-lock operations, a home agent prioritizes the servicing o... 阅读全文

posted @ 2014-09-21 23:16 CoryXie

Method and apparatus for speculative execution of uncontended lock instructions

摘要：A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually ... 阅读全文

posted @ 2014-09-18 00:40 CoryXie

Adaptively handling remote atomic execution based upon contention prediction

摘要：In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is pr... 阅读全文

posted @ 2014-09-18 00:33 CoryXie

Virtual address cache memory, processor and multiprocessor

摘要：An embodiment provides avirtualaddresscachememory including: a TLB virtualpage memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to holdcachedat... 阅读全文

posted @ 2014-09-17 12:37 CoryXie

Reentrant protected mode kernel using virtual 8086 mode interrupt service routines

摘要：A method for allowing a protected mode kernel to service, in virtual 8086 mode, hardware interrupts which occur during execution of ring 0 protected mode code. When an interrupt occurs during executio... 阅读全文

posted @ 2014-09-16 09:59 CoryXie

Flexible implementation of a system management mode (SMM) in a processor

摘要：Asystemmanagementmode(SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processin... 阅读全文

posted @ 2014-09-11 23:55 CoryXie

What is x86 Conforming Code Segment?

摘要：SRC=Microprocessor Based Systems SRC=Computer Architecture: A Quantitative Approach 阅读全文

posted @ 2014-09-11 23:03 CoryXie

Maintaining processor resources during architectural events

摘要：In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address sp... 阅读全文

posted @ 2014-09-10 00:20 CoryXie

Method and apparatus for transitioning between instruction sets in a processor

摘要：A data processor (104) is described. The data processor (104) is capable of decoding and executing a first instruction (212) of a first instruction set and a second instruction (213-219) in a second i... 阅读全文

posted @ 2014-09-09 21:16 CoryXie

Stack switching mechanism in a computer system

摘要：A method and mechanism for performing an unconditional stack switch in a processor. A processor includes a processing unit coupled to a memory. The memory includes a plurality of stacks, a special mod... 阅读全文

posted @ 2014-09-09 00:33 CoryXie

Linear to physical address translation with support for page attributes

摘要：Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support forpage attributes. In some embodiments, a system rece... 阅读全文

posted @ 2014-09-08 18:36 CoryXie

Satisfying memory ordering requirements between partial reads and non-snoop accesses

摘要：A method and apparatus for preservingmemoryordering in a cache coherent link based interconnect in light of partial and non-coherentmemoryaccesses is herein described. In one embodiment, partialm... 阅读全文

posted @ 2014-09-05 17:47 CoryXie

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随笔分类 - Computer Architecture