2022年5月14日
FPGA——INPUT DELAY
摘要： { signal:[ {name:"Clock Pad",wave:"01..0..1..0..",node:'.a'}, {name:"Data1",wave:"0.1..0..1..0..",node:'..b'}, {name:"Data2",wave:"0..3....4....5",nod 阅读全文
posted @ 2022-05-14 11:42 AdriftCore芯研社 阅读(65) 评论(0) 推荐(1)