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2005年5月15日

Notes of "Pentium Processor System Architecture" - Pentium Signal Interface (part)

摘要： 1. The Pentium processor address bus consits of two sets of signal lines: the address bus proper, consisting of 29 signal lines designated A31:A3. the Byte Enable bus, consisting of the 8 signal line... 阅读全文

posted @ 2005-05-15 23:34 bullfinch 阅读(788) 评论(0) 推荐(0) 编辑

Notes of "Pentium Processor System Architecture" - Mutiple Processors and the MESI Model

摘要： Single Processor MESI Implementation: Initial Read from System Memory: (II)[SE] L2-E L2-WB/WT#=0 L1-S First Write to the Internal Cache Line: (SE)[EM] L2-M L2-WB/WT#=1 L1-E (Write-Onc... 阅读全文

posted @ 2005-05-15 17:56 bullfinch 阅读(671) 评论(0) 推荐(0) 编辑