Design Compiler Power Simulation

Design Compiler Power Simulation

Although in a common DC flow, the power consumption is calculated and reported, it is not quite accurate since the switching probability is estimated to be some default number at the input, and the internal nets switching prob. is calculated based on the dependencies of path (See ICleaner DC No.2).

For better power consumption simulation, the SAIF file generated by the simulation procedure, which records the toggle rates based on simulation, is required during DC power reports. This md file provides some supplymentary information to the IClearner DC No.2 section, since some commands and the flow itself the blog introduced are obsolete now as the EDA tools updates.

This tutorial only covers the methods using SAIF file. The VCD file has large sizes and need further format transfer, which is not recommended.

RTL level power simulation

• Note that the RTL forward SAIF method is not applicable in Synopsys 2016 (or later).
• Note that if you are using SV file as DUT instead of Verilog file, use the "sv" parameter in command $set_gate_level_monitoring("on","sv");.
  RTL backward SAIF file is generated during VCS simulation (after the run of simv). Choose carefully of the time interval that you want to investigate.

Taking a simple adder as an example, a typical section of the testbench file is as follows:

$set_gate_level_monitoring("on","sv");
$set_toggle_region(adder_tb.i_adder);
// Choose the time interval we want to monitor
#10ms
$toggle_start();
// Wait for the finish of the simulation interval
#100ms;
$toggle_stop();
$toggle_report("adder.saif",1.0e-9,"adder_tb");

Use the -lca parameter when calling vcs command(this may not be required in later version of VCS). A typical Makefile looks like this.

.PHONY: vcs gui clean
all: clean vcs cli gui
vcs:
    bsub -Is vcs -full64 -sverilog -debug_all \
        +define+SAIF \
        -lca \
        ../../src/tb/adder_tb.sv \
        ../../src/hdl/adder.sv 
cli:
    bsub -Is ./simv
dve:
    bsub -m hmi -Is ./simv -gui &
clean:
    rm -rf ./sim.log 
    rm -rf ./csrc
    rm -rf ./DVEfiles
    rm -rf ./simv.daidir
    rm -rf ./simv
    rm -rf inter.vpd
    rm -rf ucli.key
    rm -rf *.saif

The DC scripts could be modified according to the DC UG by adding the SAIF related commands.

Gate level power simulation

We need to generate the gate-level forward SAIF file from the library. Run the following command in DC.

lib2saif -output ./lib2saif.saif path_of_your_technology_library/db/your_db.db

The VCS simulation testbench reads this SAIF file at the beginning of the simulation.

$read_lib_saif("../../lib2saif/lib2saif.saif");

The DC UG didn't give a appropriate example for gate level power simulation in DC flow. A temporary solution reuse the DC synthesis flow. This makes the environment setup easier. We delete the analyze, elaborate and compile steps. Instead, we use read_verilog to read the previously generated gate-level verilog file, and read the SAIF generated by the gate level simulation. Also, we deleted the unnecessary report commands and only apply SAIF and power related reports.

Further questions need to be answers like how to use the parasitics file, etc.