（VHDL小程序008）用VHDL设计全加器

全加器包括进位端，半加器没有进位信号端。

 

一位全加器源代码如下：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

 

entity bit1adder is

     port(

          a,b,ci:in std_logic;

          s,co:out std_logic

          );

end bit1adder;

architecture func of bit1adder is     --此功能可由真值表推出，或者亦可直接列出真值表代替此程序

signal:x,y:std_logic;

begin

     x<=a xor b;

     y<=x and ci;

     s<=x xor ci;

     co<=y or (a and b);

end func;

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二位全加器源代码如下：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all; --此包含有类型转换函数

 

entity bit2adder is

     port(

          a,b:in std_logic_vector(1 downto 0);

          ci:in std_logic;

          co:out std_logic;

          s:out std_logic_vector(1 downto 0)

          );

end bit2adder;

architecture func of bit2adder is

begin

     process(a,b,ci)                                                      --更多位的也可按照此思路来写

     variable temp:std_logic_vector(2 downto 0);

     variable x,y,sum:ingeter;

     begin

          x:=conv_integer(a);

          y:=conv_integer(b);

          sum:=(x+y)+conv_integer(ci);

          temp:=conv_std_logic_vector(sum,3);

          s<=temp(1 downto 0);

          co<=temp(2);

     end process;

end func;