摘要: 0.多看UG953,949,903 1.进入PLL/MMCM/PHASER的信号不需要做约束; 2.管脚上进来的时钟要做主时钟约束,出去的信号要做衍生时钟约束;Recommended: Define all primary clocks first. They are needed for defi 阅读全文
posted @ 2024-04-30 20:11 NoNounknow 阅读(55) 评论(0) 推荐(0)