PCI Express设备驱动 (6)

PCIe主控制器如何配置设备
设备端的定义
设备在自己的配置空间定义了自己的Capabilities list. 如果该设备支持MSI中断，在此capabilities list其中必定有一个节点的Capabilities ID=0x5D（0x5D 表明是MSI中断节点，其位置由设备自定义）.

主控制器
1> 主控制器的工作是扫描到该设备后顺藤摸瓜,沿着Capabilities List找到MSI中断节点.
 
2> 主控制器给设备上的Address Register和data register俩寄存器赋值（以MPC8548E为例，该值是中断控制器的MSI中断寄存器定义决定）;

设备
MSI中断, 本质上是一个内存写事务，该事务的payload部分都由MSI Capabilities 寄存器的值组成。

 

The key points here are:
1> Device prepare the capabilities list and the MSI node
2> Controller assign a value to the address register, which is inside the MSI capability node, and the value assigned is the kernel virtual address of the MSI interrupt description register inside the interrupt controller.
3> As well, the value assigned to the data register is defined by the MSI registers inside the interrupt controller.

 

Capabilites list 指针位于config space的 0x34 偏移量处，它是所有capabilities 节点的根节点。

*MSI如何处理一个设备有多种中断的情况！

1、MSI的格式如下：

Message Control寄存器的[6:4]和[3:1]位的定义如下：

Control[3:1]字段，对于驱动程序只读，表示当前PCIe设备要申请的中断向量号的个数。

Control[6:4]字段，对于驱动程序可读写，驱动程序写该字段，指示驱动程序为该设备申请到的中断向量号的个数。

Message Data字段的格式如下：

    每个设备的一个功能，只能有一个MSI结构，即每个功能对应一个MSI结构，每个MSI结构可获得最多32个中断向量号。MSI中断机制只能使用32个中断向量，并且这多个中断向量号必须是连续的！

   如果Control[6:4]字段的值为010，表明该设备可以使用4个中断向量号，则设备可以通过修改Message Data的第1和0比特位，生成这四个中断向量号。

PCI_LOCAL_BUS_specification_rev_2.3文档关于MSI Operation的描述：

    At configuration time, system software traverses the function’s capability list.  If a capability ID of 05h is found, the function implements MSI.  System software reads the MSI capability structure’s Message Control register to determine the function’s capabilities.

    System software reads the Multiple Message Capable field (bits 3-1 of the Message Control register) to determine the number of requested messages.  System software writes to the Multiple Message Enable field (bits 6-4 of the Message Control register) to allocate either all or a subset of the requested messages.  For example, a function can request four messages and be allocated either four, two, or one message.  The number of messages requested and allocated are aligned to a power of two (a function that requires three messages must request four).

    If the 64-bit Address Capable bit (bit 7 of the Message Control register) is set, system software initializes the MSI capability structure’s Message Address register (specifying the lower 32 bits of the message address) and the Message Upper Address register (specifying the upper 32 bits of the message address) with a system-specified message destination address.  System software may program the Message Upper Address register to zero so that the function generates a 32-bit address for the MSI write transaction.  If this bit is clear, system software initializes the MSI capability structure’s Message Address register (specifying a 32-bit message address) with a system specified message destination address.

    System software initializes the MSI capability structure’s Message Data register with a system specified message.  Care must be taken to initialize only the Message Data register (i.e., a 2-byte value) and not modify the upper two bytes of that DWORD location.

    To maintain backward compatibility, the MSI Enable bit (bit 0 of the Message Control register) is cleared after reset (MSI is disabled).  System configuration software sets this bit to enable MSI.  A device driver is prohibited from writing this bit to mask a function’s service request.  Once enabled, a function is prohibited from using its INTx# pin (if implemented) to request service (MSI and INTx# are mutually exclusive).

    Once MSI is enabled (bit 0 of the Message Control Register is set), the function may send messages.  To send a message, a function does a DWORD memory write to the address specified by the contents of the Message Address register (and optionally the Message Upper Address register for a 64-bit message address).  The DWORD that is written is made up of the value in the Message Data register in the lower two bytes and zeroes in the upper two bytes.  If the Multiple Message Enable field (bits 6-4 of the Message Control register) is non-zero, the device is permitted to modify the low order bits of the message data to generate multiple messages.  For example, a Multiple Message Enable encoding of “010” indicates the function is permitted to modify message data bits 1 and 0 to generate up to four unique messages.  If the Multiple Message Enable field is “000”, the function is not permitted to modify the message data.  How a function uses multiple messages (when allocated) is device dependent.  A function must handle being allocated less messages than requested.

    If a device signals the same message many times, only one message is guaranteed to be serviced.  If all messages must be serviced, a device driver handshake is required.  In other words, once a function signals Message A, it cannot signal Message A again until it is explicitly enabled to do so by its device driver (provided all messages must be serviced).  If some messages can be lost, a device driver handshake is not required.  For functions that support multiple messages, a function can signal multiple unique messages and is guaranteed that each unique message will be serviced.  For example, a device can signal Message A followed by Message B without any device driver handshake (both Message A and Message B will be serviced).

    An MSI is by definition a non-shared interrupt that enforces data consistency (ensures the interrupt service routine accesses the most recent data).  The system guarantees that any data written by the device prior to sending the MSI has reached its final destination before the interrupt service routine accesses that data.  Therefore, a device driver is not required to read its device before servicing its MSI.