摘要:
--第一个底层设计实体 74HC161library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity v74x161 isport( clk,clr_l,ld_l,enp,ent:in std_logic; d:in unsigned(3 downto 0); q:out unsigned(3 downto 0); rco:buffer std_logic);end v74x161;architecture v74x161_arch of v74x161 issignal iq:unsigned(3 d. 阅读全文
posted @ 2012-05-09 21:35
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