Counter及其TestBench

[从我原来的 http://chongyanglee.bokee.com 中转过来的]
本文将使用VHDL描述一个计数器及其Testbench。这应该是学习Testbench的Hello world程序吧！Testbench的书写非常灵活，可以尽情的发挥语言的特性，不需要考虑综合的要求。

严重建议看这篇文章的读者看一个计数器的从设计到仿真，里面有非常详细的代码！

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
  port(clk: in std_logic;
      reset: in std_logic;
      en: in std_logic;
      q: out std_logic_vector(3 downto 0));
end counter;

architecture behave of counter is
    signal q_n: std_logic_vector(3 downto 0);
begin
    process(clk, reset, en, q_n)
    begin
        if (reset = '1') then
            q_n <= (others => '0');--异步清零
        elsif rising_edge(clk) then
            if en = '1' then
                q_n <= q_n + 1;
            end if;
        end if;
    end process;
    q <= q_n;
end behave;

 

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity testbench is
    constant ClockPeriod: time := 40 ns;
end testbench;

architecture testbenchArc of testbench is
    component counter is
        port(clk: in std_logic;
            reset: in std_logic;
            en: in std_logic;
            q: out std_logic_vector(3 downto 0));
    end component counter;
   
    signal clock, rst, en: std_logic;
    signal q: std_logic_vector(3 downto 0);
begin
    CounterInstance: counter port map(clock, rst, en, q);
   
    simProcess: process
    begin
        rst <= '1';
        wait for 50 ns;
        rst <= '0';
        wait for 1000 ns;
        rst <= '0';
    end process simprocess;
   
    en <= '0' after 0 ns,
        '1' after 50 ns,
        '0' after 850 ns,
        '1' after 900 ns;  
   
    ClockProcess: process(clock, rst)
    begin
        if (rst = '1') then
            clock <= '0';
        else
            clock <= not clock after ClockPeriod;
        end if;
    end process ClockProcess;
   
end testbenchArc;