Cortex M0编译过程M0官方文档
编译testcase
all_gcc:
arm-none-eabi-gcc \ 生成可执行文件；
-g -O3 -mthumb \ 生成调试信息；程序优化等级；指定精简指令集，16bit；
-mcpu=cortex-m0 -mbig-endian \ 指定cpu类型；指定大端格式；
../../../../software/cmsis/Device/ARM/CMSDK_CM0/Source/GCC/startup_CMSDK_CM0.s \ .s启动文件，堆栈初始化和中断向量表；
$(TESTNAME).c \ testcase函数文件；
../../../../software/common/retarget/retarget.c \ 重定向，print输出通过uart发送出来
../../../../software/common/retarget/uart_stdout.c \ uart模块的初始化和发送函数
../../../../software/cmsis/Device/ARM/CMSDK_CM0/Source/system_CMSDK_CM0.c \ SystemInit函数，时钟初始化
-I ../../../../software/cmsis/Device/ARM/CMSDK_CM0/Include \ 指定include文件路径
-I ../../../../software/cmsis/CMSIS/Include \ 指定include文件路径
-I ../../../../software/common/retarget \指定include文件路径
-L ../../../../software/common/scripts \ 链接文件local路径
-D__STACK_SIZE=0x200 \ 宏定义栈的大小
-D__HEAP_SIZE=0x1000 \ 宏定义堆的大小
-DCORTEX_M0 \ 宏定义；
-T ../../../../software/common/scripts/cmsdk_cm0.ld \ 指定链接文件，说明flash/ram的大小和属性
-o $(TESTNAME).o 输出hello.o文件
# Generate disassembly code
arm-none-eabi-objdump -S $(TESTNAME).o > $(TESTNAME).lst elf反汇编得到的文件
# Generate binary file
arm-none-eabi-objcopy -S $(TESTNAME).o -O binary $(TESTNAME).bin 生成可执行bin文件
# Generate hex file
arm-none-eabi-objcopy -S $(TESTNAME).o -O verilog $(TESTNAME).hex 生成可执行hex文件
把二进制显示为十六进制
# Binary
all_bin: $(TESTNAME).bin
# Generate hex file from binary
od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
编译rtl文件和testcase文件
# ------- VCS -----------
# Compile RTL
compile_vcs :
vcs \
+vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug \
-f ../verilog/tbench_M0_DS.vc \
| tee compile_vcs.log
# Run simulation in batch mode
run_vcs : code
mkdir logs; \
echo quit > quit.do
./simv +vcs+lic+wait +vcs+flush+log -assert nopostproc < quit.do | tee logs/run_$(TESTNAME).log ;
# Run simulation in interactive mode
sim_vcs : code
./simv -gui +vcs+lic+wait +vcs+flush+log &
# Compile RTL, and run all tests in batch mode
all_vcs : compile_vcs bootrom
mkdir logs; \
echo quit > quit.do
for thistest in $(TEST_LIST) ; do \
make testcode TESTNAME=$$thistest ;\
./simv +vcs+lic+wait +vcs+flush+log < quit.do | tee logs/run_$$thistest.log ;\
done
# ------- Software -----------
# code target is used by other simulation targets (e.g. run_mti, sim_mti)
# Before simulation, bootrom and testcode need to be compiled.
code : testcode bootrom
# Compile test code
# Note : The use of ls after compile allows the computing server to sync up
testcode:
cd ../testcodes/$(TESTNAME) ;\
make all CPU_PRODUCT=CORTEX_M0 TOOL_CHAIN=gcc; \
cp $(TESTNAME).hex ../../rtl_sim/image.hex ; \
cd ../../rtl_sim;
# Compile bootloader
# Note : The use of ls after compile allows the computing server to sync up
bootrom:
cd ../testcodes/bootloader;\
make all CPU_PRODUCT=CORTEX_M0 TOOL_CHAIN=gcc ;\
cp bootloader.hex ../../rtl_sim/bootloader.hex ;\
cd ../../rtl_sim
# Compile all software including boot ROM
compile_all_code: bootrom
for thistest in $(TEST_LIST); do \
make testcode TESTNAME=$$thistest;\
done
编译的文件
+libext+.v+.vlib
// ============= Top level file ===============
../verilog/tb_cmsdk_mcu.v
+incdir+../verilog/
// ============= MCU Module search path =============
-y ../verilog
-y ../../../logical/cmsdk_apb_timer/verilog
-y ../../../logical/cmsdk_apb_dualtimers/verilog
-y ../../../logical/cmsdk_apb_uart/verilog
-y ../../../logical/cmsdk_apb_watchdog/verilog
-y ../../../logical/cmsdk_apb_slave_mux/verilog
-y ../../../logical/cmsdk_apb_subsystem/verilog
-y ../../../logical/cmsdk_ahb_slave_mux/verilog
-y ../../../logical/cmsdk_ahb_default_slave/verilog
-y ../../../logical/cmsdk_ahb_gpio/verilog
-y ../../../logical/cmsdk_ahb_to_apb/verilog
-y ../../../logical/models/clkgate
-y ../../../logical/models/memories/
-y ../../../logical/cmsdk_iop_gpio/verilog
+incdir+../../../logical/cmsdk_apb_dualtimers/verilog
+incdir+../../../logical/cmsdk_apb_watchdog/verilog
+incdir+../../../logical/models/memories/
// ============= Cortex-M0 Module search path =============
//Cortex M0 design start
-y ../../../cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog
-y ../../../cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog
-y ../../../cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog
-y ../../../cores/cortexm0_designstart_r1p0/logical/models/cells
+incdir+../../../cores/cortexm0_designstart_r1p0/logical/cortexm0_integration/verilog
+incdir+../../../cores/cortexm0_designstart_r1p0/logical/cortexm0_dap/verilog
+incdir+../../../cores/cortexm0_designstart_r1p0/logical/models/cells
// ============= Cortex-M0 Include file search path =============
+incdir+../../../cores/cortexm0_designstart_r1p0/logical/cortexm0ds/verilog
tb_cmsdk_mcu.v
`timescale 1ns/1ps
`include "cmsdk_mcu_defs.v"
module tb_cmsdk_mcu;
wire XTAL1; // crystal pin 1
wire XTAL2; // crystal pin 2
wire NRST; // active low reset
wire [15:0] P0; // Port 0
wire [15:0] P1; // Port 1
//Debug tester signals
wire nTRST;
wire TDI;
wire SWDIOTMS;
wire SWCLKTCK;
wire TDO;
wire PCLK; // Clock for UART capture device
wire [5:0] debug_command; // used to drive debug tester
wire debug_running; // indicate debug test is running
wire debug_err; // indicate debug test has error
wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0
// This signal is controlled by software,
// Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
// the command, use "UartPutc((char) 0x11)" to send debug test
// enable command, use "UartPutc((char) 0x12)" to send debug test
// disable command. Refer to tb_uart_capture.v file for detail
parameter BE = 0; // Big or little endian
parameter BKPT = 4; // Number of breakpoint comparators
parameter DBG = 1; // Debug configuration
parameter NUMIRQ = 32; // NUM of IRQ
parameter SMUL = 0; // Multiplier configuration
parameter SYST = 1; // SysTick
parameter WIC = 1; // Wake-up interrupt controller support
parameter WICLINES = 34; // Supported WIC lines
parameter WPT = 2; // Number of DWT comparators
// --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
cmsdk_mcu
#(.BE (BE),
.BKPT (BKPT), // Number of breakpoint comparators
.DBG (DBG), // Debug configuration
.NUMIRQ (NUMIRQ), // NUMIRQ
.SMUL (SMUL), // Multiplier configuration
.SYST (SYST), // SysTick
.WIC (WIC), // Wake-up interrupt controller support
.WICLINES (WICLINES), // Supported WIC lines
.WPT (WPT) // Number of DWT comparators
)
u_cmsdk_mcu (
.XTAL1 (XTAL1), // input
.XTAL2 (XTAL2), // output
.NRST (NRST), // active low reset
.P0 (P0),
.P1 (P1),
.nTRST (nTRST), // Not needed if serial-wire debug is used
.TDI (TDI), // Not needed if serial-wire debug is used
.TDO (TDO), // Not needed if serial-wire debug is used
.SWDIOTMS (SWDIOTMS),
.SWCLKTCK (SWCLKTCK)
);
// --------------------------------------------------------------------------------
// Source for clock and reset
// --------------------------------------------------------------------------------
cmsdk_clkreset u_cmsdk_clkreset(
.CLK (XTAL1),
.NRST (NRST)
);
// --------------------------------------------------------------------------------
// UART output capture
// --------------------------------------------------------------------------------
assign PCLK = XTAL1;
cmsdk_uart_capture u_cmsdk_uart_capture(
.RESETn (NRST),
.CLK (PCLK),
.RXD (P1[5]), // UART 2 use for StdOut
.DEBUG_TESTER_ENABLE (debug_test_en),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
// UART connection cross over for UART test
assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
// --------------------------------------------------------------------------------
// Debug tester connection -
// --------------------------------------------------------------------------------
// No debug connection for Cortex-M0 DesignStart
assign nTRST = NRST;
assign TDI = 1'b1;
assign SWDIOTMS = 1'b1;
assign SWCLKTCK = 1'b1;
bufif1 (P0[31-16], debug_running, debug_test_en);
bufif1 (P0[30-16], debug_err, debug_test_en);
pullup (debug_running);
pullup (debug_err);
// --------------------------------------------------------------------------------
// Misc
// --------------------------------------------------------------------------------
// Format for time reporting
initial $timeformat(-9, 0, " ns", 0);
endmodule
cmsdk_mcu_defs.v
//------------------------------------------------------------------------------
// Memory types
//------------------------------------------------------------------------------
`include "cmsdk_ahb_memory_models_defs.v"
// Memory types used in the Example system
// Memory wait state parameters - used by behaviorial model if applicable*/
// Boot ROM non-sequential and sequential waitstate
`define ARM_CMSDK_BOOT_MEM_WS_N 0
`define ARM_CMSDK_BOOT_MEM_WS_S 0
// ROM non-sequential and sequential waitstate
`define ARM_CMSDK_ROM_MEM_WS_N 0
`define ARM_CMSDK_ROM_MEM_WS_S 0
// RAM non-sequential and sequential waitstate
`define ARM_CMSDK_RAM_MEM_WS_N 0
`define ARM_CMSDK_RAM_MEM_WS_S 0
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