SystemVerilog中assert的用法以及asserton,assertoff和assertkill的用法

在sequence中的使用：

 class case0_sequence extends uvm_sequence #(my_transaction);
…
10   virtual task body();
…
13   repeat (10) begin
14     `uvm_do(m_trans)
15     get_response(rsp);  //
16     `uvm_info("seq", "get one response", UVM_MEDIUM)
17     rsp.print();        
18   end
或  repeat (10) begin
      `uvm_create(m_trans)//可以利用uvm_create和uvm_send的优点
      //assert(ip_tr.randomize() with {ip_tr.src_ip == 'h9999; ip_tr.dest_ip == 'h10000;}) //
      assert(m_trans.randmoize());
      p_sz = m_trans.pload.size();
      {m_trans.pload[p_sz-2],
       m_trans.pload[p_sz-1]}
      = num;
      `uvm_send(m_trans)
    end
…
22 endtask
23
24 `uvm_object_utils(case0_sequence)
25 endclass

定义在interface中使用：

interface apb_if (input clk, input rstn);
  initial begin: assertion_control
    fork
      forever begin
        wait(rstn == 0);//
        $assertoff();//
        wait(rstn == 1);//
        if(has_checks) $asserton();//
      end
    join_none
  end

endinterface : apb_if

在top_tb中的使用

module my_control ();
  initial begin : disable_assertions_during_reset
    $display ("%0t %m Disabling assertions during init..", $time);
    $assertoff (0, top_tb.cpu_rtl_1);//
    @ (top_tb.reset_n === 1'b1);//
    $display ("%0t %m Enabling assertions after init..", $time);
    $asserton (0, top_tb.cpu_rtl_1);//
   end
endmodule : my_control
module top_tb;
  logic clk =1’b0, reset_n = 1’b0;
  bus_if b_if; 
  cpu_rtl cpu_rtl_1(clk, reset_n, .*); // Instantiation of cpu module
  my_control my_control_1(); // instantiation of assertion control
..
endmodule : top_tb

SystemVerilog (SV) assertions - $assertkill or $assertoff or $asserton.

$assertoff - used to disable all assertions but allows currently active assertions to
complete before being disabled.
$assertkill - used to kill and disable all assertions including currently active assertions.
$asserton - used to turn all assertions back on

The above three assertion techniques are also popular with name of concise assertion tricks.
Designers employ them to control the enabling and disabling of all assertions in design.

Detailed discussion is covered next.
LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.


Advanced SV simulators support concise assertion techniques/approaches.

In order to implement the techniques follow the steps listed below:-

Step 1. Default clocking blocks (DCB) - The default clocking block can be used to unify the definition of ‘posedge’ to sample the digital signals. In designs with DCB the concurrent assertions can easliy inherit the sampling properties (like positive edge of sampling clock).

Example:
default clocking dcb @(posedge clk);
endclocking

Step 2. Implement ‘always’ block to disable all assertions with ‘not of reset’ else enable back.

Example:-
Always @(reset)
if (~reset) $assertkill;
else         $asserton;

Alternate approach to 1 and 2. Most simulators doesn’t support concise assertions techniques. For these simulators the engineer can implement smart macros.