windows XP下 iverilog+GTKWave使用(二)当中只有一些显示信息在终端里面,这里讲讲如何生成lxt2文件以便可以被GTKWave调用。在counter_tb.v文件里添加以下语句:

  

  1. initial  
  2.         begin             
  3.             $dumpfile("test.vcd");  
  4.             $dumpvars(0,test);  
  5.         end  


最终文件如下:

  

  1. `timescale 1ns/1ns  
  2. module test;  
  3.   
  4.     /*Make a reset that pulses once.*/  
  5.     reg reset = 0;  
  6.       
  7.     initial  
  8.         begin  
  9.             #17 reset = 1;  
  10.             #11 reset = 0;  
  11.             #29 reset = 1;  
  12.             #11 reset = 0;  
  13.             #100 $stop;  
  14.         end  
  15.       
  16.     /*Make a regular pulsing closk*/  
  17.       
  18.     reg clk = 0;  
  19.     always #5 clk = !clk;  
  20.       
  21.     wire [7:0] value;  
  22.     counter c1 (value, clk, reset);  
  23.       
  24.     initial  
  25.         $monitor("At time %t, value = %h (%0d)",$time, value, value);  
  26.     initial  
  27.         begin             
  28.             $dumpfile("test.vcd");  
  29.             $dumpvars(0,test);  
  30.         end  
  31. endmodule  


另存为counter_tb_gtk.v,然后进行下面的命令:
G:\Verilog HDL\iverilog\Demo\counter>iverilog -o test counter.v counter_tb_gtk.v

G:\Verilog HDL\iverilog\Demo\counter>ls
counter.v     counter_tb_gtk.v  my_design  test
counter_tb.v  file_list.f       mydesign

G:\Verilog HDL\iverilog\Demo\counter>vvp -n test -lxt2
LXT2 info: dumpfile test.vcd opened for output.
At time                    0, value = xx (x)
At time                   17, value = 00 (0)
At time                   35, value = 01 (1)
At time                   45, value = 02 (2)
At time                   55, value = 03 (3)
At time                   57, value = 00 (0)
At time                   75, value = 01 (1)
At time                   85, value = 02 (2)
At time                   95, value = 03 (3)
At time                  105, value = 04 (4)
At time                  115, value = 05 (5)
At time                  125, value = 06 (6)
At time                  135, value = 07 (7)
At time                  145, value = 08 (8)
At time                  155, value = 09 (9)
At time                  165, value = 0a (10)

G:\Verilog HDL\iverilog\Demo\counter>cp test.vcd test.lxt

G:\Verilog HDL\iverilog\Demo\counter>gtkwave test.lxt

posted on 2015-07-21 14:30  小光zfg  阅读(365)  评论(0)    收藏  举报