（二）启动代码分析 01
发现问题：
前面我们编写 LED 流水灯 裸机驱动，需要添加了 启动代码 （杨铸 startup.s） ,也就是初始化把 开发板带到 C 语言环境（也就是 xmain 函数）
1 ; 2 ; MDK跑马灯实验 3 ; 4 PRESERVE8 5 AREA RESET, CODE, READONLY 6 ENTRY 7 start 8 ; close watchdog 9 ldr r0, = 0x53000000 ; 将看门狗控制寄存器地址放入r0 10 mov r1, #0 11 str r1, [r0] ; 设置看门狗控制寄存器的值为0 12 13 bl initmem ; 跳转到initmem代码段，初始化内存 14 15 IMPORT xmain ; 引入xmain.c中的xmain函数 16 ldr sp, =0x34000000 ; 调用C程序之前先初始化栈指针 17 ldr lr, =endxmain ; 设置xmain函数的返回地址 18 ldr pc, =xmain ; 跳转到C程序中的xmain函数的入口处执行 19 20 endxmain 21 ldr r0, =0x56000010 ; LED的GPIO接口配置寄存器 22 ldr r1, =0x00015400 ; GPIO配置数据 23 str r1, [r0] ; 设置GPIO 24 ldr r0, =0x56000014 ; LED控制寄存器地址 25 ldr r1, =0x000000e0 ; 全部LED亮 26 str r1,[r0] 27 loop 28 b loop ; 死循环 29 30 initmem ; 内存初始化 31 ldr r0, =0x48000000 ; 加载内存相关寄存器首地址r0 32 ldr r1, =0x48000034 ; 加载内存相关寄存器尾地址到r1 33 34 adr r2, memdata ; 将寄存器配置数据地址段首地址加载到r2 35 initmemloop 36 ldr r3, [r2], #4 ; 循环设置存寄存器 37 str r3, [r0], #4 38 teq r0, r1 39 bne initmemloop ; 循环到最后一个寄存器时退出函数 40 BX lr 41 42 memdata 43 DCD 0x22000000 ;BWSCON 44 DCD 0x00000700 ;BANKCON0 45 DCD 0x00000700 ;BANKCON1 46 DCD 0x00000700 ;BANKCON2 47 DCD 0x00000700 ;BANKCON3 48 DCD 0x00000700 ;BANKCON4 49 DCD 0x00000700 ;BANKCON5 50 DCD 0x00018005 ;BANKCON6 51 DCD 0x00018005 ;BANKCON7 52 DCD 0x008e07a3 ;REFRESH 53 DCD 0x000000b1 ;BANKSIZE 54 DCD 0x00000030 ;MRSRB6 55 DCD 0x00000030 ;MRSRB7 56 57 END
现在我们尝试 用 keil 自身的 s3C2440.s
1 ;/*****************************************************************************/ 2 ;/* S3C2440.S: Startup file for Samsung S3C440 */ 3 ;/*****************************************************************************/ 4 ;/* <<< Use Configuration Wizard in Context Menu >>> */ 5 ;/*****************************************************************************/ 6 ;/* This file is part of the uVision/ARM development tools. */ 7 ;/* Copyright (c) 2005-2008 Keil Software. All rights reserved. */ 8 ;/* This software may only be used under the terms of a valid, current, */ 9 ;/* end user licence from KEIL for a compatible version of KEIL software */ 10 ;/* development tools. Nothing else gives you the right to use this software. */ 11 ;/*****************************************************************************/ 12 13 14 ;/* 15 ; * The S3C2440.S code is executed after CPU Reset. This file may be 16 ; * translated with the following SET symbols. In uVision these SET 17 ; * symbols are entered under Options - ASM - Define. 18 ; * 19 ; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock 20 ; * (used mostly when clock is already initialized from script .ini 21 ; * file). 22 ; * 23 ; * NO_MC_SETUP: when set the startup code will not initialize Memory 24 ; * Controller (used mostly when clock is already initialized from script 25 ; * .ini file). 26 ; * 27 ; * NO_GP_SETUP: when set the startup code will not initialize General Ports 28 ; * (used mostly when clock is already initialized from script .ini 29 ; * file). 30 ; * 31 ; * RAM_INTVEC: when set the startup code copies exception vectors 32 ; * from execution address to on-chip RAM. 33 ; */ 34 35 36 ; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs 37 38 Mode_USR EQU 0x10 39 Mode_FIQ EQU 0x11 40 Mode_IRQ EQU 0x12 41 Mode_SVC EQU 0x13 42 Mode_ABT EQU 0x17 43 Mode_UND EQU 0x1B 44 Mode_SYS EQU 0x1F 45 46 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled 47 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled 48 49 50 ;----------------------- Stack and Heap Definitions ---------------------------- 51 52 ;// <h> Stack Configuration (Stack Sizes in Bytes) 53 ;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> 54 ;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> 55 ;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> 56 ;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> 57 ;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> 58 ;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> 59 ;// </h> 60 61 UND_Stack_Size EQU 0x00000000 62 SVC_Stack_Size EQU 0x00000008 63 ABT_Stack_Size EQU 0x00000000 64 FIQ_Stack_Size EQU 0x00000000 65 IRQ_Stack_Size EQU 0x00000080 66 USR_Stack_Size EQU 0x00000400 67 68 ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ 69 FIQ_Stack_Size + IRQ_Stack_Size) 70 71 AREA STACK, NOINIT, READWRITE, ALIGN=3 72 73 Stack_Mem SPACE USR_Stack_Size 74 __initial_sp SPACE ISR_Stack_Size 75 Stack_Top 76 77 78 ;// <h> Heap Configuration 79 ;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> 80 ;// </h> 81 82 Heap_Size EQU 0x00000000 83 84 AREA HEAP, NOINIT, READWRITE, ALIGN=3 85 __heap_base 86 Heap_Mem SPACE Heap_Size 87 __heap_limit 88 89 90 ;----------------------- Memory Definitions ------------------------------------ 91 92 ; Internal Memory Base Addresses 93 IRAM_BASE EQU 0x40000000 94 95 96 ;----------------------- Watchdog Timer Definitions ---------------------------- 97 98 WT_BASE EQU 0x53000000 ; Watchdog Timer Base Address 99 WTCON_OFS EQU 0x00 ; Watchdog Timer Control Register Offset 100 WTDAT_OFS EQU 0x04 ; Watchdog Timer Data Register Offset 101 WTCNT_OFS EQU 0x08 ; Watchdog Timer Count Register Offset 102 103 ;// <e> Watchdog Timer Setup 104 ;// <h> Watchdog Timer Control Register (WTCON) 105 ;// <o1.8..15> Prescaler Value <0-255> 106 ;// <o1.5> Watchdog Timer Enable 107 ;// <o1.3..4> Clock Division Factor 108 ;// <0=> 16 <1=> 32 <2=> 64 <3=> 128 109 ;// <o1.2> Interrupt Generation Enable 110 ;// <o1.0> Reset Enable 111 ;// </h> 112 ;// <h> Watchdog Timer Data Register (WTDAT) 113 ;// <o2.0..15> Count Reload Value <0-65535> 114 ;// </h> 115 ;// </e> Watchdog Timer Setup 116 WT_SETUP EQU 1 117 WTCON_Val EQU 0x00000000 118 WTDAT_Val EQU 0x00008000 119 120 121 ;----------------------- Clock and Power Management Definitions ---------------- 122 123 CLOCK_BASE EQU 0x4C000000 ; Clock Base Address 124 LOCKTIME_OFS EQU 0x00 ; PLL Lock Time Count Register Offset 125 MPLLCON_OFS EQU 0x04 ; MPLL Configuration Register Offset 126 UPLLCON_OFS EQU 0x08 ; UPLL Configuration Register Offset 127 CLKCON_OFS EQU 0x0C ; Clock Generator Control Reg Offset 128 CLKSLOW_OFS EQU 0x10 ; Clock Slow Control Register Offset 129 CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset 130 CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset 131 132 ;// <e> Clock Setup 133 ;// <h> PLL Lock Time Count Register (LOCKTIME) 134 ;// <o1.16..31> U_LTIME: UPLL Lock Time Count Value for UCLK <0x0-0xFFFF> 135 ;// <o1.0..15> M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK <0x0-0xFFFF> 136 ;// </h> 137 ;// <h> MPLL Configuration Register (MPLLCON) 138 ;// <i> MPLL = (2 * m * Fin) / (p * 2^s) 139 ;// <o2.12..19> m: Main Divider m Value <9-256><#-8> 140 ;// <i> m = MDIV + 8 141 ;// <o2.4..9> p: Pre-divider p Value <3-64><#-2> 142 ;// <i> p = PDIV + 2 143 ;// <o2.0..1> s: Post Divider s Value <0-3> 144 ;// <i> s = SDIV 145 ;// </h> 146 ;// <h> UPLL Configuration Register (UPLLCON) 147 ;// <i> UPLL = ( m * Fin) / (p * 2^s) 148 ;// <o3.12..19> m: Main Divider m Value <8-263><#-8> 149 ;// <i> m = MDIV + 8 150 ;// <o3.4..9> p: Pre-divider p Value <2-65><#-2> 151 ;// <i> p = PDIV + 2 152 ;// <o3.0..1> s: Post Divider s Value <0-3> 153 ;// <i> s = SDIV 154 ;// </h> 155 ;// <h> Clock Generation Control Register (CLKCON) 156 ;// <o4.20> AC97 Enable 157 ;// <o4.19> Camera Enable 158 ;// <o4.18> SPI Enable 159 ;// <o4.17> IIS Enable 160 ;// <o4.16> IIC Enable 161 ;// <o4.15> ADC + Touch Screen Enable 162 ;// <o4.14> RTC Enable 163 ;// <o4.13> GPIO Enable 164 ;// <o4.12> UART2 Enable 165 ;// <o4.11> UART1 Enable 166 ;// <o4.10> UART0 Enable 167 ;// <o4.9> SDI Enable 168 ;// <o4.8> PWMTIMER Enable 169 ;// <o4.7> USB Device Enable 170 ;// <o4.6> USB Host Enable 171 ;// <o4.5> LCDC Enable 172 ;// <o4.4> NAND FLASH Controller Enable 173 ;// <o4.3> SLEEP Enable 174 ;// <o4.2> IDLE BIT Enable 175 ;// </h> 176 ;// <h> Clock Slow Control Register (CLKSLOW) 177 ;// <o5.7> UCLK_ON: UCLK ON 178 ;// <o5.5> MPLL_OFF: Turn off PLL 179 ;// <o5.4> SLOW_BIT: Slow Mode Enable 180 ;// <o5.0..2> SLOW_VAL: Slow Clock Divider <0-7> 181 ;// </h> 182 ;// <h> Clock Divider Control Register (CLKDIVN) 183 ;// <o6.3> DIVN_UPLL: UCLK Select 184 ;// <0=> UCLK = UPLL clock 185 ;// <1=> UCLK = UPLL clock / 2 186 ;// <o6.1..2> HDIVN: HCLK Select 187 ;// <0=> HCLK = FCLK 188 ;// <1=> HCLK = FCLK / 2 189 ;// <2=> HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8 190 ;// <3=> HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6 191 ;// <o6.0> PDIVN: PCLK Select 192 ;// <0=> PCLK = HCLK 193 ;// <1=> PCLK = HCLK / 2 194 ;// </h> 195 ;// <h> Camera Clock Divider Control Register (CAMDIVN) 196 ;// <o7.12> DVS_EN: ARM Core Clock Select 197 ;// <0=> ARM core runs at FCLK 198 ;// <1=> ARM core runs at HCLK 199 ;// <o7.9> HCLK4_HALF: HDIVN Division Rate Change Bit 200 ;// <0=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4 201 ;// <1=> If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8 202 ;// <o7.8> HCLK3_HALF: HDIVN Division Rate Change Bit 203 ;// <0=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3 204 ;// <1=> If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6 205 ;// <o7.4> CAMCLK Select 206 ;// <0=> CAMCLK = UPLL 207 ;// <1=> CAMCLK = UPLL / CAMCLK_DIV 208 ;// <o7.0..3> CAMCLK_DIV: CAMCLK Divider <0-15> 209 ;// <i> Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1)) 210 ;// <i> Divider is used only if CAMCLK_SEL = 1 211 ;// </h> 212 ;// </e> Clock Setup 213 CLOCK_SETUP EQU 0 214 LOCKTIME_Val EQU 0x0FFF0FFF 215 MPLLCON_Val EQU 0x00043011 216 UPLLCON_Val EQU 0x00038021 217 CLKCON_Val EQU 0x001FFFF0 218 CLKSLOW_Val EQU 0x00000004 219 CLKDIVN_Val EQU 0x0000000F 220 CAMDIVN_Val EQU 0x00000000 221 222 223 ;----------------------- Memory Controller Definitions ------------------------- 224 225 MC_BASE EQU 0x48000000 ; Memory Controller Base Address 226 BWSCON_OFS EQU 0x00 ; Bus Width and Wait Status Ctrl Offset 227 BANKCON0_OFS EQU 0x04 ; Bank 0 Control Register Offset 228 BANKCON1_OFS EQU 0x08 ; Bank 1 Control Register Offset 229 BANKCON2_OFS EQU 0x0C ; Bank 2 Control Register Offset 230 BANKCON3_OFS EQU 0x10 ; Bank 3 Control Register Offset 231 BANKCON4_OFS EQU 0x14 ; Bank 4 Control Register Offset 232 BANKCON5_OFS EQU 0x18 ; Bank 5 Control Register Offset 233 BANKCON6_OFS EQU 0x1C ; Bank 6 Control Register Offset 234 BANKCON7_OFS EQU 0x20 ; Bank 7 Control Register Offset 235 REFRESH_OFS EQU 0x24 ; SDRAM Refresh Control Register Offset 236 BANKSIZE_OFS EQU 0x28 ; Flexible Bank Size Register Offset 237 MRSRB6_OFS EQU 0x2C ; Bank 6 Mode Register Offset 238 MRSRB7_OFS EQU 0x30 ; Bank 7 Mode Register Offset 239 240 ;// <e> Memory Controller Setup 241 ;// <h> Bus Width and Wait Control Register (BWSCON) 242 ;// <o1.31> ST7: Use UB/LB for Bank 7 243 ;// <o1.30> WS7: Enable Wait Status for Bank 7 244 ;// <o1.28..29> DW7: Data Bus Width for Bank 7 245 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved 246 ;// <o1.27> ST6: Use UB/LB for Bank 6 247 ;// <o1.26> WS6: Enable Wait Status for Bank 6 248 ;// <o1.24..25> DW6: Data Bus Width for Bank 6 249 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved 250 ;// <o1.23> ST5: Use UB/LB for Bank 5 251 ;// <o1.22> WS5: Enable Wait Status for Bank 5 252 ;// <o1.20..21> DW5: Data Bus Width for Bank 5 253 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved 254 ;// <o1.19> ST4: Use UB/LB for Bank 4 255 ;// <o1.18> WS4: Enable Wait Status for Bank 4 256 ;// <o1.16..17> DW4: Data Bus Width for Bank 4 257 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved 258 ;// <o1.15> ST3: Use UB/LB for Bank 3 259 ;// <o1.14> WS3: Enable Wait Status for Bank 3 260 ;// <o1.12..13> DW3: Data Bus Width for Bank 3 261 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved 262 ;// <o1.11> ST2: Use UB/LB for Bank 2 263 ;// <o1.10> WS2: Enable Wait Status for Bank 2 264 ;// <o1.8..9> DW2: Data Bus Width for Bank 2 265 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved 266 ;// <o1.7> ST1: Use UB/LB for Bank 1 267 ;// <o1.6> WS1: Enable Wait Status for Bank 1 268 ;// <o1.4..5> DW1: Data Bus Width for Bank 1 269 ;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Reserved 270 ;// <o1.1..2> DW0: Indicate Data Bus Width for Bank 0 271 ;// <1=> 16-bit <2=> 32-bit 272 ;// </h> 273 ;// <h> Bank 0 Control Register (BANKCON0) 274 ;// <o2.13..14> Tacs: Address Set-up Time before nGCS 275 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 276 ;// <o2.11..12> Tcos: Chip Selection Set-up Time before nOE 277 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 278 ;// <o2.8..10> Tacc: Access Cycle 279 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks 280 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks 281 ;// <o2.6..7> Tcoh: Chip Selection Hold Time after nOE 282 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 283 ;// <o2.4..5> Tcah: Address Hold Time after nGCS 284 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 285 ;// <o2.2..3> Tacp: Page Mode Access Cycle at Page Mode 286 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks 287 ;// <o2.0..1> PMC: Page Mode Configuration 288 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data 289 ;// </h> 290 ;// <h> Bank 1 Control Register (BANKCON1) 291 ;// <o3.13..14> Tacs: Address Set-up Time before nGCS 292 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 293 ;// <o3.11..12> Tcos: Chip Selection Set-up Time before nOE 294 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 295 ;// <o3.8..10> Tacc: Access Cycle 296 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks 297 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks 298 ;// <o3.6..7> Tcoh: Chip Selection Hold Time after nOE 299 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 300 ;// <o3.4..5> Tcah: Address Hold Time after nGCS 301 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 302 ;// <o3.2..3> Tacp: Page Mode Access Cycle at Page Mode 303 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks 304 ;// <o3.0..1> PMC: Page Mode Configuration 305 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data 306 ;// </h> 307 ;// <h> Bank 2 Control Register (BANKCON2) 308 ;// <o4.13..14> Tacs: Address Set-up Time before nGCS 309 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 310 ;// <o4.11..12> Tcos: Chip Selection Set-up Time before nOE 311 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 312 ;// <o4.8..10> Tacc: Access Cycle 313 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks 314 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks 315 ;// <o4.6..7> Tcoh: Chip Selection Hold Time after nOE 316 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 317 ;// <o4.4..5> Tcah: Address Hold Time after nGCS 318 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 319 ;// <o4.2..3> Tacp: Page Mode Access Cycle at Page Mode 320 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks 321 ;// <o4.0..1> PMC: Page Mode Configuration 322 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data 323 ;// </h> 324 ;// <h> Bank 3 Control Register (BANKCON3) 325 ;// <o5.13..14> Tacs: Address Set-up Time before nGCS 326 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 327 ;// <o5.11..12> Tcos: Chip Selection Set-up Time before nOE 328 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 329 ;// <o5.8..10> Tacc: Access Cycle 330 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks 331 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks 332 ;// <o5.6..7> Tcoh: Chip Selection Hold Time after nOE 333 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 334 ;// <o5.4..5> Tcah: Address Hold Time after nGCS 335 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 336 ;// <o5.2..3> Tacp: Page Mode Access Cycle at Page Mode 337 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks 338 ;// <o5.0..1> PMC: Page Mode Configuration 339 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data 340 ;// </h> 341 ;// <h> Bank 4 Control Register (BANKCON4) 342 ;// <o6.13..14> Tacs: Address Set-up Time before nGCS 343 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 344 ;// <o6.11..12> Tcos: Chip Selection Set-up Time before nOE 345 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 346 ;// <o6.8..10> Tacc: Access Cycle 347 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks 348 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks 349 ;// <o6.6..7> Tcoh: Chip Selection Hold Time after nOE 350 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 351 ;// <o6.4..5> Tcah: Address Hold Time after nGCS 352 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 353 ;// <o6.2..3> Tacp: Page Mode Access Cycle at Page Mode 354 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks 355 ;// <o6.0..1> PMC: Page Mode Configuration 356 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data 357 ;// </h> 358 ;// <h> Bank 5 Control Register (BANKCON5) 359 ;// <o7.13..14> Tacs: Address Set-up Time before nGCS 360 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 361 ;// <o7.11..12> Tcos: Chip Selection Set-up Time before nOE 362 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 363 ;// <o7.8..10> Tacc: Access Cycle 364 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks 365 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks 366 ;// <o7.6..7> Tcoh: Chip Selection Hold Time after nOE 367 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 368 ;// <o7.4..5> Tcah: Address Hold Time after nGCS 369 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 370 ;// <o7.2..3> Tacp: Page Mode Access Cycle at Page Mode 371 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks 372 ;// <o7.0..1> PMC: Page Mode Configuration 373 ;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data 374 ;// </h> 375 ;// <h> Bank 6 Control Register (BANKCON6) 376 ;// <o8.15..16> Memory Type Selection 377 ;// <0=> ROM or SRAM <3=> SDRAM 378 ;// <o8.13..14> Tacs: Address Set-up Time before nGCS 379 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 380 ;// <o8.11..12> Tcos: Chip Selection Set-up Time before nOE 381 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 382 ;// <o8.8..10> Tacc: Access Cycle 383 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks 384 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks 385 ;// <o8.6..7> Tcoh: Chip Selection Hold Time after nOE 386 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 387 ;// <o8.4..5> Tcah: Address Hold Time after nGCS 388 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 389 ;// <o8.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay 390 ;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp, 391 ;// <i> if type is SDRAM then parameter is Trcd 392 ;// <i> For SDRAM 6 cycles setting is not allowed 393 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks 394 ;// <o8.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> 395 ;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC, 396 ;// <i> if type is SDRAM then parameter is SCAN 397 ;// </h> 398 ;// <h> Bank 7 Control Register (BANKCON7) 399 ;// <o9.15..16> Memory Type Selection 400 ;// <0=> ROM or SRAM <3=> SDRAM 401 ;// <o9.13..14> Tacs: Address Set-up Time before nGCS 402 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 403 ;// <o9.11..12> Tcos: Chip Selection Set-up Time before nOE 404 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 405 ;// <o9.8..10> Tacc: Access Cycle 406 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks 407 ;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks 408 ;// <o9.6..7> Tcoh: Chip Selection Hold Time after nOE 409 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 410 ;// <o9.4..5> Tcah: Address Hold Time after nGCS 411 ;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks 412 ;// <o9.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay 413 ;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp, 414 ;// <i> if type is SDRAM then parameter is Trcd 415 ;// <i> For SDRAM 6 cycles setting is not allowed 416 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks 417 ;// <o9.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3> 418 ;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC, 419 ;// <i> if type is SDRAM then parameter is SCAN 420 ;// </h> 421 ;// <h> SDRAM Refresh Control Register (REFRESH) 422 ;// <o10.23> REFEN: SDRAM Refresh Enable 423 ;// <o10.22> TREFMD: SDRAM Refresh Mode 424 ;// <0=> CBR/Auto Refresh <1=> Self Refresh 425 ;// <o10.20..21> Trp: SDRAM RAS Pre-charge Time 426 ;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved 427 ;// <o10.18..19> Tsrc: SDRAM Semi Row Cycle Time 428 ;// <i> SDRAM Row cycle time: Trc = Tsrc + Trp 429 ;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks 430 ;// <o10.0..10> Refresh Counter <0-1023> 431 ;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK 432 ;// </h> 433 ;// <h> Flexible Bank Size Register (BANKSIZE) 434 ;// <o11.7> BURST_EN: ARM Core Burst Operation Enable 435 ;// <o11.5> SCKE_EN: SDRAM Power Down Mode Enable 436 ;// <o11.4> SCLK_EN: SCLK Enabled During SDRAM Access Cycle 437 ;// <0=> SCLK is always active <1=> SCLK is active only during the access 438 ;// <o11.0..2> BK76MAP: BANK6 and BANK7 Memory Map 439 ;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB 440 ;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB 441 ;// <o11.0..10> Refresh Counter <0-1023> 442 ;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK 443 ;// </h> 444 ;// <h> SDRAM Mode Register Set Register 6 (MRSRB6) 445 ;// <o12.7> WBL: Write Burst Length 446 ;// <0=> Burst (Fixed) 447 ;// <o12.7..8> TM: Test Mode 448 ;// <0=> Mode register set (Fixed) 449 ;// <o12.4..6> CL: CAS Latency 450 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks 451 ;// <o12.3> BT: Burst Type 452 ;// <0=> Sequential (Fixed) 453 ;// <o12.0..2> BL: Burst Length 454 ;// <0=> 1 (Fixed) 455 ;// </h> 456 ;// <h> SDRAM Mode Register Set Register 7 (MRSRB7) 457 ;// <o13.7> WBL: Write Burst Length 458 ;// <0=> Burst (Fixed) 459 ;// <o13.7..8> TM: Test Mode 460 ;// <0=> Mode register set (Fixed) 461 ;// <o13.4..6> CL: CAS Latency 462 ;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks 463 ;// <o13.3> BT: Burst Type 464 ;// <0=> Sequential (Fixed) 465 ;// <o13.0..2> BL: Burst Length 466 ;// <0=> 1 (Fixed) 467 ;// </h> 468 ;// </e> Memory Controller Setup 469 MC_SETUP EQU 0 470 BWSCON_Val EQU 0x22000000 471 BANKCON0_Val EQU 0x00000700 472 BANKCON1_Val EQU 0x00000700 473 BANKCON2_Val EQU 0x00000700 474 BANKCON3_Val EQU 0x00000700 475 BANKCON4_Val EQU 0x00000700 476 BANKCON5_Val EQU 0x00000700 477 BANKCON6_Val EQU 0x00018005 478 BANKCON7_Val EQU 0x00018005 479 REFRESH_Val EQU 0x008404F3 480 BANKSIZE_Val EQU 0x00000032 481 MRSRB6_Val EQU 0x00000020 482 MRSRB7_Val EQU 0x00000020 483 484 485 ;----------------------- I/O Port Definitions ---------------------------------- 486 487 GPA_BASE EQU 0x56000000 ; GPA Base Address 488 GPB_BASE EQU 0x56000010 ; GPB Base Address 489 GPC_BASE EQU 0x56000020 ; GPC Base Address 490 GPD_BASE EQU 0x56000030 ; GPD Base Address 491 GPE_BASE EQU 0x56000040 ; GPE Base Address 492 GPF_BASE EQU 0x56000050 ; GPF Base Address 493 GPG_BASE EQU 0x56000060 ; GPG Base Address 494 GPH_BASE EQU 0x56000070 ; GPH Base Address 495 GPJ_BASE EQU 0x560000D0 ; GPJ Base Address 496 GPCON_OFS EQU 0x00 ; Control Register Offset 497 GPDAT_OFS EQU 0x04 ; Data Register Offset 498 GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset 499 500 ;// <e> I/O Setup 501 GP_SETUP EQU 0 502 503 ;// <e> Port A Settings 504 ;// <h> Port A Control Register (GPACON) 505 ;// <o1.22> GPA22 <0=> Output <1=> nFCE 506 ;// <o1.21> GPA21 <0=> Output <1=> nRSTOUT 507 ;// <o1.20> GPA20 <0=> Output <1=> nFRE 508 ;// <o1.19> GPA19 <0=> Output <1=> nFWE 509 ;// <o1.18> GPA18 <0=> Output <1=> ALE 510 ;// <o1.17> GPA17 <0=> Output <1=> CLE 511 ;// <o1.16> GPA16 <0=> Output <1=> nGCS[5] 512 ;// <o1.15> GPA15 <0=> Output <1=> nGCS[4] 513 ;// <o1.14> GPA14 <0=> Output <1=> nGCS[3] 514 ;// <o1.13> GPA13 <0=> Output <1=> nGCS[2] 515 ;// <o1.12> GPA12 <0=> Output <1=> nGCS[1] 516 ;// <o1.11> GPA11 <0=> Output <1=> ADDR26 517 ;// <o1.10> GPA10 <0=> Output <1=> ADDR25 518 ;// <o1.9> GPA9 <0=> Output <1=> ADDR24 519 ;// <o1.8> GPA8 <0=> Output <1=> ADDR23 520 ;// <o1.7> GPA7 <0=> Output <1=> ADDR22 521 ;// <o1.6> GPA6 <0=> Output <1=> ADDR21 522 ;// <o1.5> GPA5 <0=> Output <1=> ADDR20 523 ;// <o1.4> GPA4 <0=> Output <1=> ADDR19 524 ;// <o1.3> GPA3 <0=> Output <1=> ADDR18 525 ;// <o1.2> GPA2 <0=> Output <1=> ADDR17 526 ;// <o1.1> GPA1 <0=> Output <1=> ADDR16 527 ;// <o1.0> GPA0 <0=> Output <1=> ADDR0 528 ;// </h> 529 ;// </e> 530 GPA_SETUP EQU 0 531 GPACON_Val EQU 0x000003FF 532 533 ;// <e> Port B Settings 534 ;// <h> Port B Control Register (GPBCON) 535 ;// <o1.20..21> GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved 536 ;// <o1.18..19> GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved 537 ;// <o1.16..17> GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved 538 ;// <o1.14..15> GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved 539 ;// <o1.12..13> GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved 540 ;// <o1.10..11> GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved 541 ;// <o1.8..9> GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved 542 ;// <o1.6..7> GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved 543 ;// <o1.4..5> GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved 544 ;// <o1.2..3> GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved 545 ;// <o1.0..1> GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved 546 ;// </h> 547 ;// <h> Port B Pull-up Settings Register (GPBUP) 548 ;// <o2.10> GPB10 Pull-up Disable 549 ;// <o2.9> GPB9 Pull-up Disable 550 ;// <o2.8> GPB8 Pull-up Disable 551 ;// <o2.7> GPB7 Pull-up Disable 552 ;// <o2.6> GPB6 Pull-up Disable 553 ;// <o2.5> GPB5 Pull-up Disable 554 ;// <o2.4> GPB4 Pull-up Disable 555 ;// <o2.3> GPB3 Pull-up Disable 556 ;// <o2.2> GPB2 Pull-up Disable 557 ;// <o2.1> GPB1 Pull-up Disable 558 ;// <o2.0> GPB0 Pull-up Disable 559 ;// </h> 560 ;// </e> 561 GPB_SETUP EQU 0 562 GPBCON_Val EQU 0x00000000 563 GPBUP_Val EQU 0x00000000 564 565 ;// <e> Port C Settings 566 ;// <h> Port C Control Register (GPCCON) 567 ;// <o1.30..31> GPC15 <0=> Input <1=> Output <2=> VD[7] <3=> Reserved 568 ;// <o1.28..29> GPC14 <0=> Input <1=> Output <2=> VD[6] <3=> Reserved 569 ;// <o1.26..27> GPC13 <0=> Input <1=> Output <2=> VD[5] <3=> Reserved 570 ;// <o1.24..25> GPC12 <0=> Input <1=> Output <2=> VD[4] <3=> Reserved 571 ;// <o1.22..23> GPC11 <0=> Input <1=> Output <2=> VD[3] <3=> Reserved 572 ;// <o1.20..21> GPC10 <0=> Input <1=> Output <2=> VD[2] <3=> Reserved 573 ;// <o1.18..19> GPC9 <0=> Input <1=> Output <2=> VD[1] <3=> Reserved 574 ;// <o1.16..17> GPC8 <0=> Input <1=> Output <2=> VD[0] <3=> Reserved 575 ;// <o1.14..15> GPC7 <0=> Input <1=> Output <2=> LCD_LPCREVB <3=> Reserved 576 ;// <o1.12..13> GPC6 <0=> Input <1=> Output <2=> LCD_LPCREV <3=> Reserved 577 ;// <o1.10..11> GPC5 <0=> Input <1=> Output <2=> LCD_LPCOE <3=> Reserved 578 ;// <o1.8..9> GPC4 <0=> Input <1=> Output <2=> VM <3=> I2SSDI 579 ;// <o1.6..7> GPC3 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved 580 ;// <o1.4..5> GPC2 <0=> Input <1=> Output <2=> VLINE <3=> Reserved 581 ;// <o1.2..3> GPC1 <0=> Input <1=> Output <2=> VCLK <3=> Reserved 582 ;// <o1.0..1> GPC0 <0=> Input <1=> Output <2=> LEND <3=> Reserved 583 ;// </h> 584 ;// <h> Port C Pull-up Settings Register (GPCUP) 585 ;// <o2.15> GPC15 Pull-up Disable 586 ;// <o2.14> GPC14 Pull-up Disable 587 ;// <o2.13> GPC13 Pull-up Disable 588 ;// <o2.12> GPC12 Pull-up Disable 589 ;// <o2.11> GPC11 Pull-up Disable 590 ;// <o2.10> GPC10 Pull-up Disable 591 ;// <o2.9> GPC9 Pull-up Disable 592 ;// <o2.8> GPC8 Pull-up Disable 593 ;// <o2.7> GPC7 Pull-up Disable 594 ;// <o2.6> GPC6 Pull-up Disable 595 ;// <o2.5> GPC5 Pull-up Disable 596 ;// <o2.4> GPC4 Pull-up Disable 597 ;// <o2.3> GPC3 Pull-up Disable 598 ;// <o2.2> GPC2 Pull-up Disable 599 ;// <o2.1> GPC1 Pull-up Disable 600 ;// <o2.0> GPC0 Pull-up Disable 601 ;// </h> 602 ;// </e> 603 GPC_SETUP EQU 0 604 GPCCON_Val EQU 0x00000000 605 GPCUP_Val EQU 0x00000000 606 607 ;// <e> Port D Settings 608 ;// <h> Port D Control Register (GPDCON) 609 ;// <o1.30..31> GPD15 <0=> Input <1=> Output <2=> VD[23] <3=> nSS0 610 ;// <o1.28..29> GPD14 <0=> Input <1=> Output <2=> VD[22] <3=> nSS1 611 ;// <o1.26..27> GPD13 <0=> Input <1=> Output <2=> VD[21] <3=> Reserved 612 ;// <o1.24..25> GPD12 <0=> Input <1=> Output <2=> VD[20] <3=> Reserved 613 ;// <o1.22..23> GPD11 <0=> Input <1=> Output <2=> VD[19] <3=> Reserved 614 ;// <o1.20..21> GPD10 <0=> Input <1=> Output <2=> VD[18] <3=> SPICLK1 615 ;// <o1.18..19> GPD9 <0=> Input <1=> Output <2=> VD[17] <3=> SPIMOSI1 616 ;// <o1.16..17> GPD8 <0=> Input <1=> Output <2=> VD[16] <3=> SPIMISO1 617 ;// <o1.14..15> GPD7 <0=> Input <1=> Output <2=> VD[15] <3=> Reserved 618 ;// <o1.12..13> GPD6 <0=> Input <1=> Output <2=> VD[14] <3=> Reserved 619 ;// <o1.10..11> GPD5 <0=> Input <1=> Output <2=> VD[13] <3=> Reserved 620 ;// <o1.8..9> GPD4 <0=> Input <1=> Output <2=> VD[12] <3=> Reserved 621 ;// <o1.6..7> GPD3 <0=> Input <1=> Output <2=> VD[11] <3=> Reserved 622 ;// <o1.4..5> GPD2 <0=> Input <1=> Output <2=> VD[10] <3=> Reserved 623 ;// <o1.2..3> GPD1 <0=> Input <1=> Output <2=> VD[9] <3=> Reserved 624 ;// <o1.0..1> GPD0 <0=> Input <1=> Output <2=> VD[8] <3=> Reserved 625 ;// </h> 626 ;// <h> Port D Pull-up Settings Register (GPDUP) 627 ;// <o2.15> GPD15 Pull-up Disable 628 ;// <o2.14> GPD14 Pull-up Disable 629 ;// <o2.13> GPD13 Pull-up Disable 630 ;// <o2.12> GPD12 Pull-up Disable 631 ;// <o2.11> GPD11 Pull-up Disable 632 ;// <o2.10> GPD10 Pull-up Disable 633 ;// <o2.9> GPD9 Pull-up Disable 634 ;// <o2.8> GPD8 Pull-up Disable 635 ;// <o2.7> GPD7 Pull-up Disable 636 ;// <o2.6> GPD6 Pull-up Disable 637 ;// <o2.5> GPD5 Pull-up Disable 638 ;// <o2.4> GPD4 Pull-up Disable 639 ;// <o2.3> GPD3 Pull-up Disable 640 ;// <o2.2> GPD2 Pull-up Disable 641 ;// <o2.1> GPD1 Pull-up Disable 642 ;// <o2.0> GPD0 Pull-up Disable 643 ;// </h> 644 ;// </e> 645 GPD_SETUP EQU 0 646 GPDCON_Val EQU 0x00000000 647 GPDUP_Val EQU 0x00000000 648 649 ;// <e> Port E Settings 650 ;// <h> Port E Control Register (GPECON) 651 ;// <o1.30..31> GPE15 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved 652 ;// <i> This pad is open-drain, and has no pull-up option. 653 ;// <o1.28..29> GPE14 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved 654 ;// <i> This pad is open-drain, and has no pull-up option. 655 ;// <o1.26..27> GPE13 <0=> Input <1=> Output <2=> SPICLK0 <3=> Reserved 656 ;// <o1.24..25> GPE12 <0=> Input <1=> Output <2=> SPIMOSI0 <3=> Reserved 657 ;// <o1.22..23> GPE11 <0=> Input <1=> Output <2=> SPIMISO0 <3=> Reserved 658 ;// <o1.20..21> GPE10 <0=> Input <1=> Output <2=> SDDAT3 <3=> Reserved 659 ;// <o1.18..19> GPE9 <0=> Input <1=> Output <2=> SDDAT2 <3=> Reserved 660 ;// <o1.16..17> GPE8 <0=> Input <1=> Output <2=> SDDAT1 <3=> Reserved 661 ;// <o1.14..15> GPE7 <0=> Input <1=> Output <2=> SDDAT0 <3=> Reserved 662 ;// <o1.12..13> GPE6 <0=> Input <1=> Output <2=> SDCMD <3=> Reserved 663 ;// <o1.10..11> GPE5 <0=> Input <1=> Output <2=> SDCLK <3=> Reserved 664 ;// <o1.8..9> GPE4 <0=> Input <1=> Output <2=> I2SDO <3=> AC_SDATA_OUT 665 ;// <o1.6..7> GPE3 <0=> Input <1=> Output <2=> I2SDI <3=> AC_SDATA_IN 666 ;// <o1.4..5> GPE2 <0=> Input <1=> Output <2=> CDCLK <3=> AC_nRESET 667 ;// <o1.2..3> GPE1 <0=> Input <1=> Output <2=> I2SSCLK <3=> AC_BIT_CLK 668 ;// <o1.0..1> GPE0 <0=> Input <1=> Output <2=> I2SLRCK <3=> AC_SYNC 669 ;// </h> 670 ;// <h> Port E Pull-up Settings Register (GPEUP) 671 ;// <o2.13> GPE13 Pull-up Disable 672 ;// <o2.12> GPE12 Pull-up Disable 673 ;// <o2.11> GPE11 Pull-up Disable 674 ;// <o2.10> GPE10 Pull-up Disable 675 ;// <o2.9> GPE9 Pull-up Disable 676 ;// <o2.8> GPE8 Pull-up Disable 677 ;// <o2.7> GPE7 Pull-up Disable 678 ;// <o2.6> GPE6 Pull-up Disable 679 ;// <o2.5> GPE5 Pull-up Disable 680 ;// <o2.4> GPE4 Pull-up Disable 681 ;// <o2.3> GPE3 Pull-up Disable 682 ;// <o2.2> GPE2 Pull-up Disable 683 ;// <o2.1> GPE1 Pull-up Disable 684 ;// <o2.0> GPE0 Pull-up Disable 685 ;// </h> 686 ;// </e> 687 GPE_SETUP EQU 0 688 GPECON_Val EQU 0x00000000 689 GPEUP_Val EQU 0x00000000 690 691 ;// <e> Port F Settings 692 ;// <h> Port F Control Register (GPFCON) 693 ;// <o1.14..15> GPF7 <0=> Input <1=> Output <2=> EINT[7] <3=> Reserved 694 ;// <o1.12..13> GPF6 <0=> Input <1=> Output <2=> EINT[6] <3=> Reserved 695 ;// <o1.10..11> GPF5 <0=> Input <1=> Output <2=> EINT[5] <3=> Reserved 696 ;// <o1.8..9> GPF4 <0=> Input <1=> Output <2=> EINT[4] <3=> Reserved 697 ;// <o1.6..7> GPF3 <0=> Input <1=> Output <2=> EINT[3] <3=> Reserved 698 ;// <o1.4..5> GPF2 <0=> Input <1=> Output <2=> EINT[2] <3=> Reserved 699 ;// <o1.2..3> GPF1 <0=> Input <1=> Output <2=> EINT[1] <3=> Reserved 700 ;// <o1.0..1> GPF0 <0=> Input <1=> Output <2=> EINT[0] <3=> Reserved 701 ;// </h> 702 ;// <h> Port F Pull-up Settings Register (GPFUP) 703 ;// <o2.7> GPF7 Pull-up Disable 704 ;// <o2.6> GPF6 Pull-up Disable 705 ;// <o2.5> GPF5 Pull-up Disable 706 ;// <o2.4> GPF4 Pull-up Disable 707 ;// <o2.3> GPF3 Pull-up Disable 708 ;// <o2.2> GPF2 Pull-up Disable 709 ;// <o2.1> GPF1 Pull-up Disable 710 ;// <o2.0> GPF0 Pull-up Disable 711 ;// </h> 712 ;// </e> 713 GPF_SETUP EQU 0 714 GPFCON_Val EQU 0x00000000 715 GPFUP_Val EQU 0x00000000 716 717 ;// <e> Port G Settings 718 ;// <h> Port G Control Register (GPGCON) 719 ;// <o1.30..31> GPG15 <0=> Input <1=> Output <2=> EINT[23] <3=> Reserved 720 ;// <o1.28..29> GPG14 <0=> Input <1=> Output <2=> EINT[22] <3=> Reserved 721 ;// <o1.26..27> GPG13 <0=> Input <1=> Output <2=> EINT[21] <3=> Reserved 722 ;// <o1.24..25> GPG12 <0=> Input <1=> Output <2=> EINT[20] <3=> Reserved 723 ;// <o1.22..23> GPG11 <0=> Input <1=> Output <2=> EINT[19] <3=> TCLK[1] 724 ;// <o1.20..21> GPG10 <0=> Input <1=> Output <2=> EINT[18] <3=> nCTS1 725 ;// <o1.18..19> GPG9 <0=> Input <1=> Output <2=> EINT[17] <3=> nRTS1 726 ;// <o1.16..17> GPG8 <0=> Input <1=> Output <2=> EINT[16] <3=> Reserved 727 ;// <o1.14..15> GPG7 <0=> Input <1=> Output <2=> EINT[15] <3=> SPICLK1 728 ;// <o1.12..13> GPG6 <0=> Input <1=> Output <2=> EINT[14] <3=> SPIMOSI1 729 ;// <o1.10..11> GPG5 <0=> Input <1=> Output <2=> EINT[13] <3=> SPIMISO1 730 ;// <o1.8..9> GPG4 <0=> Input <1=> Output <2=> EINT[12] <3=> LCD_PWRDN 731 ;// <o1.6..7> GPG3 <0=> Input <1=> Output <2=> EINT[11] <3=> nSS1 732 ;// <o1.4..5> GPG2 <0=> Input <1=> Output <2=> EINT[10] <3=> nSS0 733 ;// <o1.2..3> GPG1 <0=> Input <1=> Output <2=> EINT[9] <3=> Reserved 734 ;// <o1.0..1> GPG0 <0=> Input <1=> Output <2=> EINT[8] <3=> Reserved 735 ;// </h> 736 ;// <h> Port G Pull-up Settings Register (GPGUP) 737 ;// <o2.15> GPG15 Pull-up Disable 738 ;// <o2.14> GPG14 Pull-up Disable 739 ;// <o2.13> GPG13 Pull-up Disable 740 ;// <o2.12> GPG12 Pull-up Disable 741 ;// <o2.11> GPG11 Pull-up Disable 742 ;// <o2.10> GPG10 Pull-up Disable 743 ;// <o2.9> GPG9 Pull-up Disable 744 ;// <o2.8> GPG8 Pull-up Disable 745 ;// <o2.7> GPG7 Pull-up Disable 746 ;// <o2.6> GPG6 Pull-up Disable 747 ;// <o2.5> GPG5 Pull-up Disable 748 ;// <o2.4> GPG4 Pull-up Disable 749 ;// <o2.3> GPG3 Pull-up Disable 750 ;// <o2.2> GPG2 Pull-up Disable 751 ;// <o2.1> GPG1 Pull-up Disable 752 ;// <o2.0> GPG0 Pull-up Disable 753 ;// </h> 754 ;// </e> 755 GPG_SETUP EQU 0 756 GPGCON_Val EQU 0x00000000 757 GPGUP_Val EQU 0x00000000 758 759 ;// <e> Port H Settings 760 ;// <h> Port H Control Register (GPHCON) 761 ;// <o1.20..21> GPH10 <0=> Input <1=> Output <2=> CLKOUT1 <3=> Reserved 762 ;// <o1.18..19> GPH9 <0=> Input <1=> Output <2=> CLKOUT0 <3=> Reserved 763 ;// <o1.16..17> GPH8 <0=> Input <1=> Output <2=> UEXTCLK <3=> Reserved 764 ;// <o1.14..15> GPH7 <0=> Input <1=> Output <2=> RXD[2] <3=> nCTS1 765 ;// <o1.12..13> GPH6 <0=> Input <1=> Output <2=> TXD[2] <3=> nRTS1 766 ;// <o1.10..11> GPH5 <0=> Input <1=> Output <2=> RXD[1] <3=> Reserved 767 ;// <o1.8..9> GPH4 <0=> Input <1=> Output <2=> TXD[1] <3=> Reserved 768 ;// <o1.6..7> GPH3 <0=> Input <1=> Output <2=> RXD[0] <3=> Reserved 769 ;// <o1.4..5> GPH2 <0=> Input <1=> Output <2=> TXD[0] <3=> Reserved 770 ;// <o1.2..3> GPH1 <0=> Input <1=> Output <2=> nRTS0 <3=> Reserved 771 ;// <o1.0..1> GPH0 <0=> Input <1=> Output <2=> nCTS0 <3=> Reserved 772 ;// </h> 773 ;// <h> Port H Pull-up Settings Register (GPHUP) 774 ;// <o2.10> GPH10 Pull-up Disable 775 ;// <o2.9> GPH9 Pull-up Disable 776 ;// <o2.8> GPH8 Pull-up Disable 777 ;// <o2.7> GPH7 Pull-up Disable 778 ;// <o2.6> GPH6 Pull-up Disable 779 ;// <o2.5> GPH5 Pull-up Disable 780 ;// <o2.4> GPH4 Pull-up Disable 781 ;// <o2.3> GPH3 Pull-up Disable 782 ;// <o2.2> GPH2 Pull-up Disable 783 ;// <o2.1> GPH1 Pull-up Disable 784 ;// <o2.0> GPH0 Pull-up Disable 785 ;// </h> 786 ;// </e> 787 GPH_SETUP EQU 0 788 GPHCON_Val EQU 0x00000000 789 GPHUP_Val EQU 0x00000000 790 791 ;// <e> Port J Settings 792 ;// <h> Port J Control Register (GPJCON) 793 ;// <o1.24..25> GPJ12 <0=> Input <1=> Output <2=> CAMRESET <3=> Reserved 794 ;// <o1.22..23> GPJ11 <0=> Input <1=> Output <2=> CAMCLKOUT <3=> Reserved 795 ;// <o1.20..21> GPJ10 <0=> Input <1=> Output <2=> CAMHREF <3=> Reserved 796 ;// <o1.18..19> GPJ9 <0=> Input <1=> Output <2=> CAMVSYNC <3=> Reserved 797 ;// <o1.16..17> GPJ8 <0=> Input <1=> Output <2=> CAMPCLK <3=> Reserved 798 ;// <o1.14..15> GPJ7 <0=> Input <1=> Output <2=> CAMDATA[7] <3=> Reserved 799 ;// <o1.12..13> GPJ6 <0=> Input <1=> Output <2=> CAMDATA[6] <3=> Reserved 800 ;// <o1.10..11> GPJ5 <0=> Input <1=> Output <2=> CAMDATA[5] <3=> Reserved 801 ;// <o1.8..9> GPJ4 <0=> Input <1=> Output <2=> CAMDATA[4] <3=> Reserved 802 ;// <o1.6..7> GPJ3 <0=> Input <1=> Output <2=> CAMDATA[3] <3=> Reserved 803 ;// <o1.4..5> GPJ2 <0=> Input <1=> Output <2=> CAMDATA[2] <3=> Reserved 804 ;// <o1.2..3> GPJ1 <0=> Input <1=> Output <2=> CAMDATA[1] <3=> Reserved 805 ;// <o1.0..1> GPJ0 <0=> Input <1=> Output <2=> CAMDATA[0] <3=> Reserved 806 ;// </h> 807 ;// <h> Port J Pull-up Settings Register (GPJUP) 808 ;// <o2.12> GPJ12 Pull-up Disable 809 ;// <o2.11> GPJ11 Pull-up Disable 810 ;// <o2.10> GPJ10 Pull-up Disable 811 ;// <o2.9> GPJ9 Pull-up Disable 812 ;// <o2.8> GPJ8 Pull-up Disable 813 ;// <o2.7> GPJ7 Pull-up Disable 814 ;// <o2.6> GPJ6 Pull-up Disable 815 ;// <o2.5> GPJ5 Pull-up Disable 816 ;// <o2.4> GPJ4 Pull-up Disable 817 ;// <o2.3> GPJ3 Pull-up Disable 818 ;// <o2.2> GPJ2 Pull-up Disable 819 ;// <o2.1> GPJ1 Pull-up Disable 820 ;// <o2.0> GPJ0 Pull-up Disable 821 ;// </h> 822 ;// </e> 823 GPJ_SETUP EQU 0 824 GPJCON_Val EQU 0x00000000 825 GPJUP_Val EQU 0x00000000 826 827 ;// </e> I/O Setup 828 829 830 ;----------------------- CODE -------------------------------------------------- 831 832 PRESERVE8 833 834 835 ; Area Definition and Entry Point 836 ; Startup Code must be linked first at Address at which it expects to run. 837 838 AREA RESET, CODE, READONLY 839 ARM 840 841 IF :LNOT::DEF:__EVAL 842 IMPORT ||Image$$ER_ROM1$$RO$$Length|| 843 IMPORT ||Image$$RW_RAM1$$RW$$Length|| 844 ENDIF 845 846 ; Exception Vectors 847 ; Mapped to Address 0. 848 ; Absolute addressing mode must be used. 849 ; Dummy Handlers are implemented as infinite loops which can be modified. 850 851 Vectors LDR PC, Reset_Addr 852 LDR PC, Undef_Addr 853 LDR PC, SWI_Addr 854 LDR PC, PAbt_Addr 855 LDR PC, DAbt_Addr 856 IF :DEF:__EVAL 857 DCD 0x4000 858 ELSE 859 DCD ||Image$$ER_ROM1$$RO$$Length||+\ 860 ||Image$$RW_RAM1$$RW$$Length|| 861 ENDIF 862 LDR PC, IRQ_Addr 863 LDR PC, FIQ_Addr 864 865 IF :DEF:__RTX 866 IMPORT SWI_Handler 867 IMPORT IRQ_Handler_RTX 868 ENDIF 869 870 871 Reset_Addr DCD Reset_Handler 872 Undef_Addr DCD Undef_Handler 873 SWI_Addr DCD SWI_Handler 874 PAbt_Addr DCD PAbt_Handler 875 DAbt_Addr DCD DAbt_Handler 876 DCD 0 ; Reserved Address 877 IF :DEF:__RTX 878 IRQ_Addr DCD IRQ_Handler_RTX 879 ELSE 880 IRQ_Addr DCD IRQ_Handler 881 ENDIF 882 FIQ_Addr DCD FIQ_Handler 883 884 Undef_Handler B Undef_Handler 885 IF :DEF:__RTX 886 ELSE 887 SWI_Handler B SWI_Handler 888 ENDIF 889 PAbt_Handler B PAbt_Handler 890 DAbt_Handler B DAbt_Handler 891 IRQ_Handler PROC 892 EXPORT IRQ_Handler [WEAK] 893 B . 894 ENDP 895 FIQ_Handler B FIQ_Handler 896 897 898 ; Reset Handler 899 900 EXPORT Reset_Handler 901 Reset_Handler 902 903 904 ; Watchdog Setup --------------------------------------------------------------- 905 906 IF WT_SETUP != 0 907 LDR R0, =WT_BASE 908 LDR R1, =WTCON_Val 909 LDR R2, =WTDAT_Val 910 STR R2, [R0, #WTCNT_OFS] 911 STR R2, [R0, #WTDAT_OFS] 912 STR R1, [R0, #WTCON_OFS] 913 ENDIF 914 915 916 ; Clock Setup ------------------------------------------------------------------ 917 918 IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) 919 LDR R0, =CLOCK_BASE 920 LDR R1, =LOCKTIME_Val 921 STR R1, [R0, #LOCKTIME_OFS] 922 MOV R1, #CLKDIVN_Val 923 STR R1, [R0, #CLKDIVN_OFS] 924 LDR R1, =CAMDIVN_Val 925 STR R1, [R0, #CAMDIVN_OFS] 926 LDR R1, =MPLLCON_Val 927 STR R1, [R0, #MPLLCON_OFS] 928 LDR R1, =UPLLCON_Val 929 STR R1, [R0, #UPLLCON_OFS] 930 MOV R1, #CLKSLOW_Val 931 STR R1, [R0, #CLKSLOW_OFS] 932 LDR R1, =CLKCON_Val 933 STR R1, [R0, #CLKCON_OFS] 934 ENDIF 935 936 937 ; Memory Controller Setup ------------------------------------------------------ 938 939 IF (:LNOT:(:DEF:NO_MC_SETUP)):LAND:(CLOCK_SETUP != 0) 940 LDR R0, =MC_BASE 941 LDR R1, =BWSCON_Val 942 STR R1, [R0, #BWSCON_OFS] 943 LDR R1, =BANKCON0_Val 944 STR R1, [R0, #BANKCON0_OFS] 945 LDR R1, =BANKCON1_Val 946 STR R1, [R0, #BANKCON1_OFS] 947 LDR R1, =BANKCON2_Val 948 STR R1, [R0, #BANKCON2_OFS] 949 LDR R1, =BANKCON3_Val 950 STR R1, [R0, #BANKCON3_OFS] 951 LDR R1, =BANKCON4_Val 952 STR R1, [R0, #BANKCON4_OFS] 953 LDR R1, =BANKCON5_Val 954 STR R1, [R0, #BANKCON5_OFS] 955 LDR R1, =BANKCON6_Val 956 STR R1, [R0, #BANKCON6_OFS] 957 LDR R1, =BANKCON7_Val 958 STR R1, [R0, #BANKCON7_OFS] 959 LDR R1, =REFRESH_Val 960 STR R1, [R0, #REFRESH_OFS] 961 MOV R1, #BANKSIZE_Val 962 STR R1, [R0, #BANKSIZE_OFS] 963 MOV R1, #MRSRB6_Val 964 STR R1, [R0, #MRSRB6_OFS] 965 MOV R1, #MRSRB7_Val 966 STR R1, [R0, #MRSRB7_OFS] 967 ENDIF 968 969 970 ; I/O Pins Setup --------------------------------------------------------------- 971 972 IF (:LNOT:(:DEF:NO_GP_SETUP)):LAND:(GP_SETUP != 0) 973 974 IF GPA_SETUP != 0 975 LDR R0, =GPA_BASE 976 LDR R1, =GPACON_Val 977 STR R1, [R0, #GPCON_OFS] 978 ENDIF 979 980 IF GPB_SETUP != 0 981 LDR R0, =GPB_BASE 982 LDR R1, =GPBCON_Val 983 STR R1, [R0, #GPCON_OFS] 984 LDR R1, =GPBUP_Val 985 STR R1, [R0, #GPUP_OFS] 986 ENDIF 987 988 IF GPC_SETUP != 0 989 LDR R0, =GPC_BASE 990 LDR R1, =GPCCON_Val 991 STR R1, [R0, #GPCON_OFS] 992 LDR R1, =GPCUP_Val 993 STR R1, [R0, #GPUP_OFS] 994 ENDIF 995 996 IF GPD_SETUP != 0 997 LDR R0, =GPD_BASE 998 LDR R1, =GPDCON_Val 999 STR R1, [R0, #GPCON_OFS] 1000 LDR R1, =GPDUP_Val 1001 STR R1, [R0, #GPUP_OFS] 1002 ENDIF 1003 1004 IF GPE_SETUP != 0 1005 LDR R0, =GPE_BASE 1006 LDR R1, =GPECON_Val 1007 STR R1, [R0, #GPCON_OFS] 1008 LDR R1, =GPEUP_Val 1009 STR R1, [R0, #GPUP_OFS] 1010 ENDIF 1011 1012 IF GPF_SETUP != 0 1013 LDR R0, =GPF_BASE 1014 LDR R1, =GPFCON_Val 1015 STR R1, [R0, #GPCON_OFS] 1016 LDR R1, =GPFUP_Val 1017 STR R1, [R0, #GPUP_OFS] 1018 ENDIF 1019 1020 IF GPG_SETUP != 0 1021 LDR R0, =GPG_BASE 1022 LDR R1, =GPGCON_Val 1023 STR R1, [R0, #GPCON_OFS] 1024 LDR R1, =GPGUP_Val 1025 STR R1, [R0, #GPUP_OFS] 1026 ENDIF 1027 1028 IF GPH_SETUP != 0 1029 LDR R0, =GPH_BASE 1030 LDR R1, =GPHCON_Val 1031 STR R1, [R0, #GPCON_OFS] 1032 LDR R1, =GPHUP_Val 1033 STR R1, [R0, #GPUP_OFS] 1034 ENDIF 1035 1036 IF GPJ_SETUP != 0 1037 LDR R0, =GPJ_BASE 1038 LDR R1, =GPJCON_Val 1039 STR R1, [R0, #GPCON_OFS] 1040 LDR R1, =GPJUP_Val 1041 STR R1, [R0, #GPUP_OFS] 1042 ENDIF 1043 1044 ENDIF 1045 1046 1047 ; Copy Exception Vectors to Internal RAM --------------------------------------- 1048 1049 IF :DEF:RAM_INTVEC 1050 ADR R8, Vectors ; Source 1051 LDR R9, =IRAM_BASE ; Destination 1052 LDMIA R8!, {R0-R7} ; Load Vectors 1053 STMIA R9!, {R0-R7} ; Store Vectors 1054 LDMIA R8!, {R0-R7} ; Load Handler Addresses 1055 STMIA R9!, {R0-R7} ; Store Handler Addresses 1056 ENDIF 1057 1058 1059 ; Setup Stack for each mode ---------------------------------------------------- 1060 1061 LDR R0, =Stack_Top 1062 1063 ; Enter Undefined Instruction Mode and set its Stack Pointer 1064 MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit 1065 MOV SP, R0 1066 SUB R0, R0, #UND_Stack_Size 1067 1068 ; Enter Abort Mode and set its Stack Pointer 1069 MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit 1070 MOV SP, R0 1071 SUB R0, R0, #ABT_Stack_Size 1072 1073 ; Enter FIQ Mode and set its Stack Pointer 1074 MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit 1075 MOV SP, R0 1076 SUB R0, R0, #FIQ_Stack_Size 1077 1078 ; Enter IRQ Mode and set its Stack Pointer 1079 MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit 1080 MOV SP, R0 1081 SUB R0, R0, #IRQ_Stack_Size 1082 1083 ; Enter Supervisor Mode and set its Stack Pointer 1084 MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit 1085 MOV SP, R0 1086 SUB R0, R0, #SVC_Stack_Size 1087 1088 ; Enter User Mode and set its Stack Pointer 1089 MSR CPSR_c, #Mode_USR 1090 MOV SP, R0 1091 SUB SL, SP, #USR_Stack_Size 1092 1093 ; Enter User Mode and set its Stack Pointer 1094 MSR CPSR_c, #Mode_USR 1095 IF :DEF:__MICROLIB 1096 1097 EXPORT __initial_sp 1098 1099 ELSE 1100 1101 MOV SP, R0 1102 SUB SL, SP, #USR_Stack_Size 1103 1104 ENDIF 1105 1106 1107 ; Enter the C code ------------------------------------------------------------- 1108 1109 IMPORT main 1110 LDR R0, =main 1111 BX R0 1112 1113 1114 IF :DEF:__MICROLIB 1115 1116 EXPORT __heap_base 1117 EXPORT __heap_limit 1118 1119 ELSE 1120 ; User Initial Stack & Heap 1121 AREA |.text|, CODE, READONLY 1122 1123 IMPORT __use_two_region_memory 1124 EXPORT __user_initial_stackheap 1125 __user_initial_stackheap 1126 1127 LDR R0, = Heap_Mem 1128 LDR R1, =(Stack_Mem + USR_Stack_Size) 1129 LDR R2, = (Heap_Mem + Heap_Size) 1130 LDR R3, = Stack_Mem 1131 BX LR 1132 ENDIF 1133 1134 1135 END
但是不能编译不通过，怎么办呢，麻痹的
解决方案：
原来函数要修改一下：
把__main 改成 mian , 当然 主函数 xmain() 也要改成 main（） ，这样就可以了，当然可以仿真，就是不要老用 JLNK 可以直接用软件仿真
如下：
成功了，现在我们接下来继续开始 启动代码的讲解！！！！！！LOL
