带帧同步检测的RS232通信

其中 data_process模块：

module data_process
(
    clk,
    valid,
    rst_n,
    data_from_sp,
    data_out,
    flag,
    clr,    
    data_out_en
);

 input    clk;
 input    valid/*synthesis keep*/;
 input    rst_n;
input    [9:0] data_from_sp/*synthesis keep*/;

output    [7:0] data_out;
output  data_out_en;
output  clr;
output  [3:0] flag;

reg        [3:0] flag;
reg        [7:0] data_out_r;
reg        data_out_en/*synthesis noprune*/;

always @ (posedge clk or negedge rst_n)
begin
    if (!rst_n)
        begin
            data_out_r <= 8'b1111_1111;
            data_out_en <= 1'b0;
            flag <= 4'b0000;
        end
    else if (valid)
        begin
            if((data_from_sp[9]==1'b1)&&(data_from_sp[0]==1'b0)||(flag!=4'b0000))
                begin                        
                    if(flag==4'b0000)
                        begin
                            data_out_r[7:0] <= data_from_sp[8:1];
                            data_out_en <= 1'b1;
                            flag <= flag +1'b1;
                        end
                    else if(flag==4'd9)
                        begin
                            flag <= 4'b0000;
                            data_out_en <= 1'b0;
                            data_out_r <= 8'b1111_1111;
                        end    
                    else 
                        begin
                            flag <= flag +1'b1;
                            data_out_en <= 1'b0;
                            data_out_r <= 8'b1111_1111;
                        end
                end
            else
                begin
                    data_out_r <= 8'b1111_1111;
                    data_out_en <= 1'b0;
                    
                end 
        end
    else
        begin
            data_out_r <= 8'b1111_1111;
            data_out_en <= 1'b0;
            flag <= 4'b0000;
        end 
end
assign data_out = data_out_r;


reg [3:0] cnt;
reg clr;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
    begin
        cnt <= 4'b0000;
        clr <=1'b1;
    end
else if (data_out_en)    
        cnt <= cnt +1'b1;
else if ((cnt>=4'd5)&&(cnt<=4'd10))
    begin
        cnt<=cnt +1'b1;
        clr<=1'b0;
    end
else if (cnt==4'd11)
    begin
        cnt <= 4'b0000;
        clr <=1'b1;
    end
end

endmodule 

data_to_reg模块

module data_to_reg
(
    clk,
    valid,
    rst_n,
    data,
    OUT_A,
    OUT_B,
    OUT_C,
    OUT_D
);

input    clk;
input    valid;
input   rst_n;
input    [7:0] data;

output    reg [7:0] OUT_A;
output    reg [7:0] OUT_B;
output    reg [7:0] OUT_C;
output    reg [7:0] OUT_D;
reg         [2:0] cnt;

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
        cnt <= 3'b000;
else if(valid)
        cnt <= cnt +1'b1;
else if (cnt==3'd5)
        begin
        cnt <= 3'b000;
        
        end
end

always@ (posedge valid)
begin
    case (cnt)
        3'd1: 
            begin 
                OUT_A <= data;
                //OUT_B<=8'b1111_1111;
                //OUT_C<=8'b1111_1111;
                //OUT_D<=8'b1111_1111;
            end
        3'd2: 
            begin 
                //OUT_A <= 8'b1111_1111;
                OUT_B<=data;
                //OUT_C<=8'b1111_1111;
                //OUT_D<=8'b1111_1111;
            end
        3'd3: 
            begin 
                //OUT_A <= 8'b1111_1111;
                //OUT_B<=8'b1111_1111;
                OUT_C<=data;
                //OUT_D<=8'b1111_1111;
            end
        3'd4: 
            begin 
                //OUT_A <= 8'b1111_1111;
                //OUT_B<=8'b1111_1111;
                //OUT_C<=8'b1111_1111;
                OUT_D<=data;
            end
        default: 
            begin 
                OUT_A <= 8'b1111_1111;
                OUT_B<=8'b1111_1111;
                OUT_C<=8'b1111_1111;
                OUT_D<=8'b1111_1111;
            end
    endcase
end

endmodule