Verilog error and warnings

1、Warning (12125): Using design file div.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project原因：模块不是在本项目生成的，而是直接copy了别的项目的原理图和源程序而生成的，而不是用QUARTUS将文件添加进本项目
措施：无须理会，不影响使用
2、Warning (10230): Verilog HDL assignment warning at sdram_control_4port.v(368): truncated value with size 32 to match size of target (10)数值不指定位宽的话，会被默认成32位，不影响使用

3、Warning (10240): Verilog HDL Always Construct warning at sdram_control_4port.v(406): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct

解释：信号被综合成了latch，锁存器的EN和数据输入端口存在一个竞争的问题

措施：将计数器从里面抽出来

4、Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(26): truncated literal to match 1 bits

5、Warning (10275): Verilog HDL Module Instantiation warning at SDRAM_HR_HW.v(121): ignored dangling comma in List of Port Connections

6、Warning (15400): WYSIWYG primitive "Sdram_Control_4Port:u0|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_87o1:auto_generated|altsyncram_mf51:fifo_ram|ram_block13a0" has a port clk0 that is stuck at GND

7、Warning (21074): Design contains 3 input pin(s) that do not drive logic
 Warning (15610): No output dependent on input pin "KEY[1]"
 Warning (15610): No output dependent on input pin "KEY[2]"
 Warning (15610): No output dependent on input pin "KEY[3]"

8.Error: Verilog HDL Module Instantiation error at DAC8.v(21): cannot connect instance ports

both by order and by name.

原因：例化时信号前没有加点“.”,如：keypad key_inst ( .clk(clksys),rst_n(rst_n),，，）；rst_n信号前没点。