multiplication----overview

High speed multipliers are typically classified into two categories. The first,known as parallel multiplication, involves the use of hardware to multiply a
m-bit number by a n-bit number to completely produce a n+m product. Parallel multipliers can also be pipelined to reduce the cycle time and increase the
throughput by introducing storage elements within the multiplier. On the other hand, serial or sequential multipliers compute the product sequentially usually
utilizing storage elements so that hardware of the multiplier is reused during an iteration. The implementations presented in this chapter are primarily parallel
multipliers since they usually provide the most benefit to a computer architecture at the expense of area. However, many of the designs presented here can
be utilized in a sequential fashion as well.

Multiplication usually involve three separate steps as listed below. Although ere are implementations that can theoretically be reduced to the generation
 the shifted multiples of the multiplicand and multi-operand addition (i.e.e addition of more than two operands), most multipliers utilize the steps below. Although there are various different perspectives on the implementation of multiplication, its basic entity usually is the adder.
1 Partial Product (PP) Generation - utilizes a collection of gates to generate the partial product bits (i.e. ai · bi).
2 Partial Product (PP) Reduction - utilizes adders (counters) to reduce the partial products to sum and carry vectors.
3 Final Carry-Propagate Addition (CPA) - adds the sum and carry vectors to produce the product.