2022年12月30日
HDLBits--Verilog习题记录4
摘要： 4.Circuits Sequential Logic Latches and Flip-Flops Edge capture register 问题描述： For each bit in a 32-bit vector, capture when the input signal changes 阅读全文
posted @ 2022-12-30 17:22 傅红雪a 阅读(133) 评论(0) 推荐(0)
HDLBits--Verilog习题记录3
摘要： 3.Circuits Sequential Logic Latches and Flip-Flops Detect an edge 问题描述： For each bit in an 8-bit vector, detect when the input signal changes from 0 i 阅读全文
posted @ 2022-12-30 15:48 傅红雪a 阅读(175) 评论(0) 推荐(0)
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