摘要: 例如:某数据手册中写道The address line ADD is asserted at time t1 and is deasserteed at time t2.接下来给出的时序图中可以看出,ADD信号在t1时变成高电平,t2时变为低电平.我们可以译为:"地址线ADD在t1时有效,在t2时无 阅读全文
posted @ 2023-09-06 12:30 Swingfall 阅读(364) 评论(0) 推荐(0)