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GENERATE It is another concurrent statement (along with operators and WHEN). Itis equivalent to the sequential statement LOOP in the sense that ital... 阅读全文
posted @ 2015-05-20 23:39
mengdie
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WHEN (simple and selected) It is one of the fundamental concurrent statements (alongwith operators and GENERATE). It appears in two forms: WHEN / EL... 阅读全文
posted @ 2015-05-20 22:07
mengdie
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Using operators Operators can be used to implement any combinational circuit. However, as willbecome apparent later, complex circuits are usually eas... 阅读全文
posted @ 2015-05-20 21:56
mengdie
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Examples1) Force input1 to 0 at the current simulator time. force input1 02) Force the fourth element of the array bus1 to 1 at the current simulat... 阅读全文
posted @ 2015-05-20 17:24
mengdie
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force This command allows you to apply stimulus interactively to VHDL signals(not variables), Verilog nets and registers, and SystemC boundary types.... 阅读全文
posted @ 2015-05-20 14:59
mengdie
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