#include "config.h"
#include "CONFIG_FPGA_ALL.h"
#include "xparameters.h"
#include "xil_io.h"
#include "sleep.h"
#include "ad9361_api.h"
#include "ad9361.h"
#include "xil_printf.h"
double param[10];
extern struct ad9361_rf_phy *ad9361_phy;
#define CONFIG_FPGA_ALL_BASEADDR XPAR_CONFIG_FPGA_ALL_0_S00_AXI_BASEADDR
#define cfg_universal_port_addr 0x5c
#define cfg_universal_port_data 0x60
extern void cfg_universal(uint32_t addr,uint32_t data);
void cfg_universal(uint32_t addr,uint32_t data)
{
CONFIG_FPGA_ALL_mWriteReg((CONFIG_FPGA_ALL_BASEADDR) ,cfg_universal_port_addr,addr);
CONFIG_FPGA_ALL_mWriteReg((CONFIG_FPGA_ALL_BASEADDR) ,cfg_universal_port_data,data);
usleep(1);
}
void set_register(double* param, char param_no) // "register?" command
{
uint16_t reg_addr;
uint8_t reg_val;
struct spi_device spi;
if(param_no >= 1)
{
spi.id_no = 0;
reg_addr =(uint16_t) param[0];
reg_val =(uint8_t)param[1];
ad9361_spi_write(&spi, reg_addr,reg_val);
// xil_printf("write register[0x%x]=0x%x\r\n", reg_addr, reg_val);
}
}
void get_register(double* param, char param_no) // "register?" command
{
uint16_t reg_addr;
uint8_t reg_val;
struct spi_device spi;
if(param_no >= 1)
{
spi.id_no = 0;
reg_addr = param[0];
reg_val = ad9361_spi_read(&spi, reg_addr);
// if((reg_val != 0x02) && (reg_val != 0x82) && (reg_val != 0x42))
// {
// xil_printf("/************************************\r\n");
// xil_printf("register[0x%x]=0x%x\r\n", reg_addr, reg_val);
// xil_printf("/************************************\r\n");
// }
xil_printf("register[0x%x]=0x%x\r\n", reg_addr, reg_val);
}
}
/**************************************************************************//***
* @brief Gets current RX LO frequency [MHz].
*
* @return None.
*******************************************************************************/
void get_rx_lo_freq(double* param, char param_no) // "rx_lo_freq?" command
{
uint64_t lo_freq_hz;
ad9361_get_rx_lo_freq(ad9361_phy, &lo_freq_hz);
lo_freq_hz /= 1000000;
xil_printf("rx_lo_freq=%d\n", (uint32_t)lo_freq_hz);
}
/**************************************************************************//***
* @brief Sets the RX LO frequency [MHz].
*
* @return None.
*******************************************************************************/
void set_rx_lo_freq(double* param, char param_no) // "rx_lo_freq=" command
{
uint64_t lo_freq_hz;
if(param_no >= 1)
{
lo_freq_hz = param[0];
lo_freq_hz *= 1000000;
ad9361_set_rx_lo_freq(ad9361_phy, lo_freq_hz);
lo_freq_hz /= 1000000;
xil_printf("rx_lo_freq=%d\n", (uint32_t)lo_freq_hz);
}
}
/**************************************************************************//***
* @brief Gets current TX LO frequency [MHz].
*
* @return None.
*******************************************************************************/
void get_tx_lo_freq(double* param, char param_no) // "tx_lo_freq?" command
{
uint64_t lo_freq_hz;
ad9361_get_tx_lo_freq(ad9361_phy, &lo_freq_hz);
lo_freq_hz /= 1000000;
xil_printf("tx_lo_freq=%d\n", (uint32_t)lo_freq_hz);
}
/**************************************************************************//***
* @brief Sets the TX LO frequency [MHz].
*
* @return None.
*******************************************************************************/
void set_tx_lo_freq(double* param, char param_no) // "tx_lo_freq=" command
{
uint64_t lo_freq_hz;
if(param_no >= 1)
{
lo_freq_hz = param[0];
lo_freq_hz *= 1000000;
ad9361_set_tx_lo_freq(ad9361_phy, lo_freq_hz);
lo_freq_hz /= 1000000;
xil_printf("tx_lo_freq=%d\n", (uint32_t)lo_freq_hz);
}
}
void init_ad9361_rf(void)
{
int status=0;
// status=ad9361_set_no_ch_mode(ad9361_phy,3);
// xil_printf("ad9361_set_no_ch_mode=%d\r\n",status);
ad9361_set_rx_rf_port_input(ad9361_phy,A_BALANCED);
status=ad9361_en_dis_tx(ad9361_phy,3,3);
xil_printf("set_tx chan status=%d\r\n",status);
status=ad9361_en_dis_rx(ad9361_phy,3,3);
xil_printf("set_rx chan status=%d\r\n",status);
uint32_t freq_rx_rf_bw;
ad9361_set_rx_rf_bandwidth(ad9361_phy,56000000);
ad9361_get_rx_rf_bandwidth(ad9361_phy,&freq_rx_rf_bw);
printf("***********rx_rf_bw=%ld hz\n",freq_rx_rf_bw);
ad9361_set_tx_rf_bandwidth(ad9361_phy,56000000);
ad9361_get_tx_rf_bandwidth(ad9361_phy,&freq_rx_rf_bw);
printf("***********tx_rf_bw=%ld hz\n",freq_rx_rf_bw);
//122880000 61440000
status=ad9361_set_trx_clock_chain_freq(ad9361_phy,61.44*1000000);
xil_printf("ad9361_set_trx_clock_chain_freq status=%d\r\n",status);
param[0]=1000; //set tx lo
set_tx_lo_freq(param, 2);
get_tx_lo_freq(param,2);
param[0]=1000; //set rx lo
set_rx_lo_freq(param, 2);
get_rx_lo_freq(param,2);
param[0]=0x006;
param[1]=0x05;
set_register(param, 3);
get_register(param,2);
param[0]=0x007;
param[1]=0x70;
set_register(param, 3);
get_register(param,2);
ad9361_set_rx_gain_control_mode(ad9361_phy,0,RF_GAIN_MGC);
ad9361_set_rx_gain_control_mode(ad9361_phy,1,RF_GAIN_MGC);
ad9361_set_rx_rf_gain(ad9361_phy,0,20);
ad9361_set_rx_rf_gain(ad9361_phy,1,20);
}
void cal_delay_ad9361_data(float freq)
{
init_ad9361_rf();
int status;
//122880000 61440000
status=ad9361_set_trx_clock_chain_freq(ad9361_phy,freq*1000000);
xil_printf("ad9361_set_trx_clock_chain_freq status=%ds\r\n",status);
xil_printf("cal freq = %llu\n", freq*1000000);
#define sig_num 50
int i=0,j=0,k=0;
int cnt_num=20;
int first_data_num_temp=100;
int flag=0;
uint32_t send_data[sig_num];
uint32_t recv_data[sig_num];
uint32_t recv_data_t[sig_num];
for(i=0;i<sig_num;i=i+1)
{
send_data[i]=((rand()) & 0xFFFFFF);
}
uint8_t delay_tab[31]={0x60,0x70,0x50,0x80,0x40,0x90,0x30,0xA0,0x20,0xB0,0x10,0xC0,0x0D,0xE0,0x00,0xD0,0xF0,
0x06,0x07,0x05,0x08,0x04,0x09,0x03,0x0A,0x02,0x0B,0x01,0x0C,0x0E,0x0F};
cfg_universal(18,3);
cfg_universal(17,sig_num);
cfg_universal(18,1);
for (i=0;i<sig_num;i++)
{
cfg_universal(15,i);
cfg_universal(16,send_data[i]);
usleep(1);
// xil_printf("%d = %x \r\n",i,send_data[i]);
}
cfg_universal(18,2);
param[0]=0x3f4;
// param[1]=0x0B;
param[1]=0x00;
set_register(param, 3);
get_register(param,2);
param[0]=0x3f5;
// param[1]=0x00;
param[1]=0xC1;
set_register(param, 3);
get_register(param,2);
param[0]=0x3f6;
param[1]=0x00;
set_register(param, 3);
get_register(param,2);
//while(1);
cfg_universal(19,1);
//while(1);
#define ADC_DELAY_REG_SWEEP
#ifdef ADC_DELAY_REG_SWEEP
printf("\r\nhex:");
uint8_t exti;
for(exti = 0; exti < 31; exti++)
{
printf("%2x ", delay_tab[exti]);
}
printf("\r\n");
#endif
for ( j = 0; j < 31; j++)
{
#ifdef ADC_DELAY_REG_SWEEP
printf("%2x: ", delay_tab[j]);
#endif
for (i = 0; i < 31; i++)
{
// for(k =0 ;k<=4;k++)
// {
first_data_num_temp=100;
param[0]=0x006;
param[1]=delay_tab[i];
set_register(param, 3);
// get_register(param,2);
param[0]=0x007;
param[1]=delay_tab[j];
set_register(param, 3);
// get_register(param,2);
// param[0]=0x011;
// param[1]=k;
// set_register(param, 3);
// get_register(param,2);
cfg_universal(21,1);
cnt_num=20;
while(cnt_num--)
{
status=CONFIG_FPGA_ALL_mReadReg(CONFIG_FPGA_ALL_BASEADDR,0x0A*4);
// xil_printf("\r\nmdlt state = %d\r\n",status);
if(status==4)
{
break;
}
}
for(cnt_num=0;cnt_num<sig_num;cnt_num++)
{
cfg_universal(20,cnt_num);
recv_data[cnt_num]=CONFIG_FPGA_ALL_mReadReg(CONFIG_FPGA_ALL_BASEADDR,9*4);
// xil_printf("\r\nmdlt state = %x\r\n",recv_data[cnt_num]);
if(recv_data[cnt_num] == send_data[0] )
{
first_data_num_temp=cnt_num;
// xil_printf("&&&&&&&&%d\r\n",first_data_num_temp);
}
}
int temp=0;
for(cnt_num=0;cnt_num<sig_num;cnt_num++)
{
if(first_data_num_temp==100)
{
// cnt_num=sig_num;
flag = -1;
break;
}
else
{
recv_data_t[cnt_num]=recv_data[first_data_num_temp+temp];
temp=temp+1;
if((first_data_num_temp+temp)>=sig_num)
{
first_data_num_temp=0;
temp=0;
}
flag = 0;
}
}
for(cnt_num=0;cnt_num<sig_num;cnt_num++)
{
if(flag<0)
{
// cnt_num=sig_num;
flag = -1;
break;
}
else
{
if(recv_data_t[cnt_num] == send_data[cnt_num])
{
flag = 1;
}
else
{
flag = -1;
break;
}
}
}
// if(flag == 1)
// {
// xil_printf("Calibration delay data successful \r\n");
// goto my_goto;
// break;
// }
if(flag == 1)
{
printf(" O ");
}
else
{
printf(" # ");
}
cfg_universal(21,3);
// }
}
printf("\n");
}
if((i==31) && (j==31))
{
cfg_universal(19,0);
xil_printf("Calibration delay data failed \r\n");
}
my_goto:
cfg_universal(19,0);
param[0]=0x3f5;
param[1]=0x00;
set_register(param, 3);
// get_register(param,2);
}
