modelsim testbench测试DFF触发器verilog

module tb_DFF ( clk, d, q ); input clk; input d; output q; reg q; always @ (posedge clk) q <= d; endmodule

测试文件：

`timescale 1ns / 1ps module ttbb_DFF; // Inputs reg clk; reg d; // Outputs wire q; // Instantiate the Unit Under Test (UUT) tb_DFF uut ( .clk(clk), .d(d), .q(q) ); initial begin // Initialize Inputs clk = 0; d = 0; // Wait 100 ns for global reset to finish #100; d = 1; #100; d = 0; // Add stimulus here end always begin #10 clk = ~clk; end endmodule