二期项目记录
方案定义
器件选择
原理设计仿真
原理图库绘制
原理图
封装库
PCB绘制
输出光绘文件
编写代码
焊接板子
测试连通性
调试程序
*****************************************选型结果***********************************
LCD
1.44 TFT
按键
微动开关6*6*5
旋转编码器
360度 Arduino 旋转编码器模块 FOR ARDUINO Arduino模块
FPGA
STEP-Board
DAC
AD9760ARUZ-ND——125MHz AD8047ARZ-ND
DAC辅助
PWM
LPF椭圆
无源7阶
VGA
AD603ARZ——±5V供电
DC offset
AD826ARZ-ND
PWM LPF
TL072B
衰减器
电阻,精密电阻9:1 ---0603
放大器
TL072B
MUX模拟开关
SN74LVC1G3157-DCK
缓冲滤波运放
TL072B
MCU
CC3200
DC/DC
LT3471EDD
AMS1117,---SOT-223
79L05---SOT-89
*****************************************框图设计***********************************
****************************************椭圆滤波器仿真***********************************
//AD8047输出阻抗 :0.2R
//AD603输入阻抗 :100R
//
//
//
//
滤波器仿真时,输入输出阻抗计算错误导致信号传输不到后级,输入阻抗过小导致电流过大
AD8047输出阻抗计算
AD603输入阻抗为100R(查看手册)
则使用filter soulution 产生滤波器电路
参数设置
电路和频谱
实际元件参数,由于元件实际值的不连续性,以及优先手头有的值和值的归一化处理原则,修改值并仿真
实际值频谱仿真
可以看到已经很好了
****************************************ADC前滤波器仿真***********************************
---------
****************************************原理图库建立***********************************
lcd 、、、
key 、、、
encoder
FPGA 、、、
AD9760ARUZ 、、、
AD8047ARZ 、、、
AD603ARZ 、、、
BNC 、、、
TL072B 、、、
SN74LVC1G3157- DBV 、、、
CC3200 、、、
LT3471 、、、
AMS1117 、、、
79L05 、、、
****************************************原理图绘制***********************************
确定需不需要分图纸,怎么分块
原理图库绘制,同时绘制封装库。库进行分类管理,善于利用官方库二次编辑
原理图符合的管脚顺序不一定非要按照实际。封装的尺寸一定要选好,手工焊的话焊盘要长些,画完要1:1打印到纸上器件放上去看有没有问题。
原理图符号放置
把所有要用到的原理图符号按照原理图布局大概摆放到原理图上,芯片,连接件等
电阻电容电感二极管等,各拖放一个横向一个纵向的放到原理图一角,
把参数栏填好(partnumber,manufacture),要显示的设好,标号位置调整好,封装选好。
然后接下来要用到这些就从这拖就行 (按住shift)
原理图层次
确定需不需要层次,确定层次,确定
层次原理图中的端口要注意,电源和地的符合的不需要端口(全局的)
逐块完成原理图,参考数据手册典型应用,具体指标研读数据手册中的具体项。
检查原理图
检查连接完整性
检查网络标号
检查电器连接,搭接等
检查电路正确性,参考电路图,数据手册典型图等
电源的负载能力
检查逻辑正确性
器件电源滤波电容的个数
DRC
优化布局
调整布局,合理利用空间
根据信号流向优化摆放位置
调整标号等,注释标号
器件标号的正确性位置,电阻电容电感二极管等标号的位置、统一性(u和uF、4K7和4.7K、大小写等)
元件的具体型号(AMS1117加-5表示5V的)partnumber标完整了没
阻容器件把一些对值不敏感的地方都换成一些必要的值,方便购买节省成本。电容的极性
进行必要注解
电源旁路电容不能放一堆,放在每个器件旁边,或者标出是哪个的。能清楚看出哪个电容接哪
放置测试点
放置指示灯等,考虑后续焊接,调试,使用时需要的
再次检查
对于错误提示,要逐条看,警告也要仔细看。
错误提示可以百度,一般能找到很好的解答
生成BOM
填写partnumber,manufacture,footprint,value,quatity等
导入PCB
编译完原理图若没有问题,则可以点 设计--更新到PCB
PCB封装
导入后首先检查各个元件的封装,有问题的回到原理图更改封装,库里找不到的封装自己画
画封装可以添加进已有库或新建库(在库管理里边右键一个元件EDIT是个很方便的技巧)
库按照元件类型分类,或按照公司目录再按类型分类
layout
按照小模块先摆放在一块,尽量摆放为正方,拼接时省地方。
先放电容,电容远了不起作用了,电阻无所谓。滤波电容可以打孔放背面
电源分割
双屏幕最好,或把原理图生成PDF放在手机平版上看,对照着在PCB界面一个一个搜元件号
快捷键,J--C---输入元件号,如C13,U12
然后可以先把小模块进行细化,再调整整体布局
布线
电源分割,根据电源脉络先在焊盘旁打孔,然后在电源层连接,各个电源完成后并且信号布线也完成后进行铺铜
地平面分割
同样是先在器件旁打孔连接,再用线在地平面连接,待信号线布线完成后,进行铺铜
信号线
信号线细,电源线粗(需要满足电流要求),对于阻抗有要求的场合对线宽和长度要进行计算。顶层和底层布线要垂直布线。
顶层
底层
3D
编写代码
CC3200
FPGA
总体设计
硬件功能测试,为了测试硬件的良好性,避免后续问题,此步骤很有必要
焊接调试
一、电源部分
输入5V输出±5V正常
图为加测试输入
正电压
负电压不够
换了一个79L05,好些了。淘宝买的果然不行
空载测试OK,
但带载能力似乎不足
+5的负载能力测试 —5的负载能力
AD8047 5.8 mA Typical Supply Current
TL072 2.5 mA
AD603 20 mA
AD826 7.5 mA
预计不是电源部分问题,电源负载能力正常。在用万用表串入测电流时,电流35ma,电流表上压降3V左右,电源板正常。而把电源板直接接到改电源就会出问题,发烫,应该是电流过大
二、DAC输出测试
输出一个10M的方波
先测试滤波器前的波形
代码如下:
1 /*-------------------------------------------------------------------------------------- 2 -- Filename ﹕ dac.v 3 -- Author ﹕tony-ning 4 -- Description ﹕DAC硬件测试 ,10M方波,AD9760 5 -- Called by ﹕Top module 6 -- Revision History ﹕15-10-16 7 -- Revision 1.0 8 -- Company ﹕ 9 -- Copyright(c) All right reserved 10 ---------------------------------------------------------------------------------------*/ 11 12 13 module dac 14 ( 15 input CLK, //100MHz 16 output reg[9:0]date_out 17 ); 18 19 20 21 reg [15:0]count2; 22 23 always @( posedge CLK)//CLK 10M square wave 24 begin 25 if(count2==9) 26 count2<=0; 27 else count2<=count2+1; 28 29 if(count2>=0 && count2<=5) 30 date_out<=10'h3ff; 31 else date_out<=10'h000; 32 end 33 34 35 36 endmodule
利用rom存放波形表进行仿真
1 /*-------------------------------------------------------------------------------------- 2 -- Filename ﹕ dac.v 3 -- Author ﹕tony-ning 4 -- Description ﹕DAC硬件测试 ,10M方波,AD9760 5 -- Called by ﹕Top module 6 -- Revision History ﹕15-10-16 7 -- Revision 1.0 8 -- Company ﹕ 9 -- Copyright(c) All right reserved 10 ---------------------------------------------------------------------------------------*/ 11 12 13 module dac 14 ( 15 input CLK25, // 16 output CLK_DA, 17 output [9:0]date_out 18 ); 19 20 21 22 23 /*DDS DDS_uut 24 ( 25 .clk_in(CLK), //clock in 26 .rst_n_in(1'b1), //reset, active low 27 .dds_en_in(1), //dds work enable 28 .f_increment(24'h599999), //frequency increment 29 .p_increment(0), //phase increment 30 .dac_clk_out(CLK_DA), //clock out 31 .dac_data_out(date_out) //data out 32 );*/ 33 34 35 36 37 38 reg [9:0]count2; 39 40 always @( negedge CLK)//CLK 10M square wave 41 begin 42 if(count2>=1023) 43 count2<=count2-1024; 44 else count2<=count2+100; 45 end 46 47 assign CLK_DA=CLK; 48 49 pll PLL100M 50 ( 51 .CLKI(CLK25), 52 .CLKOP(CLK) 53 ); 54 55 rom_sin sin 56 ( 57 .Address(count2), 58 .OutClock(CLK), 59 .OutClockEn(1'b1), 60 .Reset(1'b0), 61 .Q(date_out) 62 ); 63 64 65 endmodule
控制ROM循环输出1024个点
DDS输出代码(未done)
1 /************************************************** 2 module: DDS 3 author: wanganran 4 description: Direct Digital Synthesizer, generate sin signal with 10 bits dac 5 input: clk_in, rst_n_in, dds_en_in, f_increment, p_increment 6 output: dac_clk_out, dac_data_out 7 date: 2015.11.05 8 **************************************************/ 9 module DDS 10 ( 11 input clk_in, //clock in 12 input rst_n_in, //reset, active low 13 input dds_en_in, //dds work enable 14 input [23:0] f_increment, //frequency increment 15 input [23:0] p_increment, //phase increment 16 output dac_clk_out, //clock out 17 output [9:0] dac_data_out //data out 18 ); 19 20 reg [23:0] phase_accumulator; 21 wire [9:0] phase; 22 //wire [9:0] dac_data_out; 23 assign dac_clk_out = clk_in; 24 25 //next_phase = phase_accumulator + f_increment; 26 always @(posedge clk_in or negedge rst_n_in) 27 begin 28 if(!rst_n_in) phase_accumulator <= 23'b0; 29 else if(dds_en_in) phase_accumulator <= phase_accumulator + f_increment; 30 end 31 32 assign phase = phase_accumulator[23:14] + p_increment; // phase is the high 8 bits 33 lookup_table lookup_table_uut 34 ( 35 .phase(phase), 36 .dac_data_out(dac_data_out) 37 ); 38 39 endmodule 40 41 /************************************************** 42 module: lookup_table 43 **************************************************/ 44 module lookup_table 45 ( 46 input [9:0] phase, 47 output reg [9:0] dac_data_out 48 ); 49 50 wire [7:0] address = phase[7:0]; 51 wire [1:0] sel = phase[9:8]; 52 wire [9:0] sine; 53 54 always@(sel or sine) 55 case (sel) 56 2'b00 : dac_data_out = {1'b1, sine[9:1]}; 57 2'b01 : dac_data_out = {1'b1, sine[9:1]}; 58 2'b10 : dac_data_out = {1'b0, 9'h1ff-sine[9:1]}; 59 2'b11 : dac_data_out = {1'b0, 9'h1ff-sine[9:1]}; 60 endcase 61 62 sine_table sine_table_uut 63 ( 64 .sel(sel), 65 .address(address), 66 .sine(sine) 67 ); 68 69 endmodule 70 71 /************************************************** 72 module: sine_table 73 **************************************************/ 74 module sine_table 75 ( 76 input [1:0] sel, 77 input [7:0] address, 78 output reg [9:0] sine 79 ); 80 81 reg [7:0] table_addr; 82 83 always @(sel or address) 84 case (sel) 85 2'b00: table_addr = address; 86 2'b01: table_addr = 8'hff - address; 87 2'b10: table_addr = address; 88 2'b11: table_addr = 8'hff - address; 89 endcase 90 91 always @(table_addr) 92 case(table_addr) 93 8'h00: sine=10'd0; 94 8'h01: sine=10'd6; 95 8'h02: sine=10'd13; 96 8'h03: sine=10'd19; 97 8'h04: sine=10'd25; 98 8'h05: sine=10'd31; 99 8'h06: sine=10'd38; 100 8'h07: sine=10'd44; 101 8'h08: sine=10'd50; 102 8'h09: sine=10'd57; 103 8'h0A: sine=10'd63; 104 8'h0B: sine=10'd69; 105 8'h0C: sine=10'd75; 106 8'h0D: sine=10'd82; 107 8'h0E: sine=10'd88; 108 8'h0F: sine=10'd94; 109 8'h10: sine=10'd100; 110 8'h11: sine=10'd107; 111 8'h12: sine=10'd113; 112 8'h13: sine=10'd119; 113 8'h14: sine=10'd125; 114 8'h15: sine=10'd132; 115 8'h16: sine=10'd138; 116 8'h17: sine=10'd144; 117 8'h18: sine=10'd150; 118 8'h19: sine=10'd156; 119 8'h1A: sine=10'd163; 120 8'h1B: sine=10'd169; 121 8'h1C: sine=10'd175; 122 8'h1D: sine=10'd181; 123 8'h1E: sine=10'd187; 124 8'h1F: sine=10'd194; 125 8'h20: sine=10'd200; 126 8'h21: sine=10'd206; 127 8'h22: sine=10'd212; 128 8'h23: sine=10'd218; 129 8'h24: sine=10'd224; 130 8'h25: sine=10'd230; 131 8'h26: sine=10'd237; 132 8'h27: sine=10'd243; 133 8'h28: sine=10'd249; 134 8'h29: sine=10'd255; 135 8'h2A: sine=10'd261; 136 8'h2B: sine=10'd267; 137 8'h2C: sine=10'd273; 138 8'h2D: sine=10'd279; 139 8'h2E: sine=10'd285; 140 8'h2F: sine=10'd291; 141 8'h30: sine=10'd297; 142 8'h31: sine=10'd303; 143 8'h32: sine=10'd309; 144 8'h33: sine=10'd315; 145 8'h34: sine=10'd321; 146 8'h35: sine=10'd327; 147 8'h36: sine=10'd333; 148 8'h37: sine=10'd339; 149 8'h38: sine=10'd345; 150 8'h39: sine=10'd351; 151 8'h3A: sine=10'd357; 152 8'h3B: sine=10'd363; 153 8'h3C: sine=10'd369; 154 8'h3D: sine=10'd374; 155 8'h3E: sine=10'd380; 156 8'h3F: sine=10'd386; 157 8'h40: sine=10'd392; 158 8'h41: sine=10'd398; 159 8'h42: sine=10'd403; 160 8'h43: sine=10'd409; 161 8'h44: sine=10'd415; 162 8'h45: sine=10'd421; 163 8'h46: sine=10'd426; 164 8'h47: sine=10'd432; 165 8'h48: sine=10'd438; 166 8'h49: sine=10'd443; 167 8'h4A: sine=10'd449; 168 8'h4B: sine=10'd455; 169 8'h4C: sine=10'd460; 170 8'h4D: sine=10'd466; 171 8'h4E: sine=10'd472; 172 8'h4F: sine=10'd477; 173 8'h50: sine=10'd483; 174 8'h51: sine=10'd488; 175 8'h52: sine=10'd494; 176 8'h53: sine=10'd499; 177 8'h54: sine=10'd505; 178 8'h55: sine=10'd510; 179 8'h56: sine=10'd516; 180 8'h57: sine=10'd521; 181 8'h58: sine=10'd526; 182 8'h59: sine=10'd532; 183 8'h5A: sine=10'd537; 184 8'h5B: sine=10'd543; 185 8'h5C: sine=10'd548; 186 8'h5D: sine=10'd553; 187 8'h5E: sine=10'd558; 188 8'h5F: sine=10'd564; 189 8'h60: sine=10'd569; 190 8'h61: sine=10'd574; 191 8'h62: sine=10'd579; 192 8'h63: sine=10'd584; 193 8'h64: sine=10'd590; 194 8'h65: sine=10'd595; 195 8'h66: sine=10'd600; 196 8'h67: sine=10'd605; 197 8'h68: sine=10'd610; 198 8'h69: sine=10'd615; 199 8'h6A: sine=10'd620; 200 8'h6B: sine=10'd625; 201 8'h6C: sine=10'd630; 202 8'h6D: sine=10'd635; 203 8'h6E: sine=10'd640; 204 8'h6F: sine=10'd645; 205 8'h70: sine=10'd650; 206 8'h71: sine=10'd654; 207 8'h72: sine=10'd659; 208 8'h73: sine=10'd664; 209 8'h74: sine=10'd669; 210 8'h75: sine=10'd674; 211 8'h76: sine=10'd678; 212 8'h77: sine=10'd683; 213 8'h78: sine=10'd688; 214 8'h79: sine=10'd692; 215 8'h7A: sine=10'd697; 216 8'h7B: sine=10'd702; 217 8'h7C: sine=10'd706; 218 8'h7D: sine=10'd711; 219 8'h7E: sine=10'd715; 220 8'h7F: sine=10'd720; 221 8'h80: sine=10'd724; 222 8'h81: sine=10'd729; 223 8'h82: sine=10'd733; 224 8'h83: sine=10'd737; 225 8'h84: sine=10'd742; 226 8'h85: sine=10'd746; 227 8'h86: sine=10'd750; 228 8'h87: sine=10'd755; 229 8'h88: sine=10'd759; 230 8'h89: sine=10'd763; 231 8'h8A: sine=10'd767; 232 8'h8B: sine=10'd771; 233 8'h8C: sine=10'd775; 234 8'h8D: sine=10'd779; 235 8'h8E: sine=10'd784; 236 8'h8F: sine=10'd788; 237 8'h90: sine=10'd792; 238 8'h91: sine=10'd796; 239 8'h92: sine=10'd799; 240 8'h93: sine=10'd803; 241 8'h94: sine=10'd807; 242 8'h95: sine=10'd811; 243 8'h96: sine=10'd815; 244 8'h97: sine=10'd819; 245 8'h98: sine=10'd822; 246 8'h99: sine=10'd826; 247 8'h9A: sine=10'd830; 248 8'h9B: sine=10'd834; 249 8'h9C: sine=10'd837; 250 8'h9D: sine=10'd841; 251 8'h9E: sine=10'd844; 252 8'h9F: sine=10'd848; 253 8'hA0: sine=10'd851; 254 8'hA1: sine=10'd855; 255 8'hA2: sine=10'd858; 256 8'hA3: sine=10'd862; 257 8'hA4: sine=10'd865; 258 8'hA5: sine=10'd868; 259 8'hA6: sine=10'd872; 260 8'hA7: sine=10'd875; 261 8'hA8: sine=10'd878; 262 8'hA9: sine=10'd882; 263 8'hAA: sine=10'd885; 264 8'hAB: sine=10'd888; 265 8'hAC: sine=10'd891; 266 8'hAD: sine=10'd894; 267 8'hAE: sine=10'd897; 268 8'hAF: sine=10'd900; 269 8'hB0: sine=10'd903; 270 8'hB1: sine=10'd906; 271 8'hB2: sine=10'd909; 272 8'hB3: sine=10'd912; 273 8'hB4: sine=10'd915; 274 8'hB5: sine=10'd917; 275 8'hB6: sine=10'd920; 276 8'hB7: sine=10'd923; 277 8'hB8: sine=10'd926; 278 8'hB9: sine=10'd928; 279 8'hBA: sine=10'd931; 280 8'hBB: sine=10'd934; 281 8'hBC: sine=10'd936; 282 8'hBD: sine=10'd939; 283 8'hBE: sine=10'd941; 284 8'hBF: sine=10'd944; 285 8'hC0: sine=10'd946; 286 8'hC1: sine=10'd948; 287 8'hC2: sine=10'd951; 288 8'hC3: sine=10'd953; 289 8'hC4: sine=10'd955; 290 8'hC5: sine=10'd958; 291 8'hC6: sine=10'd960; 292 8'hC7: sine=10'd962; 293 8'hC8: sine=10'd964; 294 8'hC9: sine=10'd966; 295 8'hCA: sine=10'd968; 296 8'hCB: sine=10'd970; 297 8'hCC: sine=10'd972; 298 8'hCD: sine=10'd974; 299 8'hCE: sine=10'd976; 300 8'hCF: sine=10'd978; 301 8'hD0: sine=10'd980; 302 8'hD1: sine=10'd982; 303 8'hD2: sine=10'd983; 304 8'hD3: sine=10'd985; 305 8'hD4: sine=10'd987; 306 8'hD5: sine=10'd989; 307 8'hD6: sine=10'd990; 308 8'hD7: sine=10'd992; 309 8'hD8: sine=10'd993; 310 8'hD9: sine=10'd995; 311 8'hDA: sine=10'd996; 312 8'hDB: sine=10'd998; 313 8'hDC: sine=10'd999; 314 8'hDD: sine=10'd1000; 315 8'hDE: sine=10'd1002; 316 8'hDF: sine=10'd1003; 317 8'hE0: sine=10'd1004; 318 8'hE1: sine=10'd1006; 319 8'hE2: sine=10'd1007; 320 8'hE3: sine=10'd1008; 321 8'hE4: sine=10'd1009; 322 8'hE5: sine=10'd1010; 323 8'hE6: sine=10'd1011; 324 8'hE7: sine=10'd1012; 325 8'hE8: sine=10'd1013; 326 8'hE9: sine=10'd1014; 327 8'hEA: sine=10'd1015; 328 8'hEB: sine=10'd1016; 329 8'hEC: sine=10'd1016; 330 8'hED: sine=10'd1017; 331 8'hEE: sine=10'd1018; 332 8'hEF: sine=10'd1018; 333 8'hF0: sine=10'd1019; 334 8'hF1: sine=10'd1020; 335 8'hF2: sine=10'd1020; 336 8'hF3: sine=10'd1021; 337 8'hF4: sine=10'd1021; 338 8'hF5: sine=10'd1022; 339 8'hF6: sine=10'd1022; 340 8'hF7: sine=10'd1022; 341 8'hF8: sine=10'd1023; 342 8'hF9: sine=10'd1023; 343 8'hFA: sine=10'd1023; 344 8'hFB: sine=10'd1024; 345 8'hFC: sine=10'd1024; 346 8'hFD: sine=10'd1024; 347 8'hFE: sine=10'd1024; 348 8'hFF: sine=10'd1024; 349 350 endcase 351 endmodule
8位DA输出信噪比应该为40dB
10位DA应该有60dB,但是只有40多,问题暂时没找到
开始信号质量很差,看频谱发现很多
频谱仪图形
DA输出端,可以看出在100那块有差频出来的
AD8047输出端,放大后的频谱
7阶椭圆滤波器输出,频谱看着也比较好了,但是信噪比只有40dB左右,不够,10位DA应该是60才对。verilog代码已经检验过没有问题。不知道问题在哪
滤波器的截止频率设置40M,100MSa,60-100M会有产生信号的镜像,以及差频信号,在频谱中需要去除这些
所以40M-60M就是留给滤波器的非理想的余量
电路中DAC差分输出中接的电容C12的作用不容忽视,它要抑制高频,如下图
没加C12
加上C12 ,82pF
最终输出
AD603用11K方波做控制信号,纹波20mV左右,效果
然后AD826,输出结果
至此,信号源通路就打通了,最终输出如图。当然还得匹配一下BNC50阻抗
示波器通路中,①:偏置电压由于选用电阻值较小,被运放输入电阻影响了。直接变成100倍的了
②:输入衰减倍数被运放输入阻抗影响,加了一级跟随隔离
模拟开关电源选用了数字电源,导致干扰进入。换为模拟电源了
滤波器输出也OK,至此,示波器通路也OK了