verilog 入门程序
module decode(data_in,EN,data_out)//4to16译码
input[3:0] data_in;
input EN;
output[6:0] data_out;
reg[6:0]data_out;
always(data_in or EN)
begin
data_out=7'b1111111;
if(EN==1)
case(data_in)
4'b0000:data_out=7'b0111111; //0
4'b0001:data_out=7'b0000110; //1
4'b0010:data_out=7'b1011011; //2
4'b0011:data_out=7'b1001111; //3
4'b0100:data_out=7'b1100110; //4
4'b0101:data_out=7'b1101101; //5
4'b0110:data_out=7'b1111101; //6
4'b0111:data_out=7'b0000111; //7
4'b1000:data_out=7'b1111111; //8
4'b1001:data_out=7'b1101111; //9
4'b1010:data_out=7'b0001000; //A
4'b1011:data_out=7'b0000011; //B
4'b1100:data_out=7'b0100111; //C
4'b1101:data_out=7'b0100001; //D
4'b1110:data_out=7'b0000110; //E
4'b1111:data_out=7'b0001110; //F
default: data_out=7'b1111111;
endcase
end
endmodule
/////////////////////////////////////////
module dff(Q,D,CLK); //该触发器只有信号输入端、输出端和时钟
output Q;
input D,CLK;
reg Q;
always@(posedge CLK)
begin
Q<=D;
end
endmodule
////////////////////////////////////////
module dff(Q,Qn,D,CLK,Set,Reset);
input D,CLK,Set,Reset;
output Q,Qn;
reg Q,Qn;
always@(posedge CLK or negedge Set or negedge Reset)
begin
if(!Reset) begin Q<=0;Qn<=1;end //异步清0, 低电平有效
else if(Set) begin Q<=1;Qn<=0;end //异步置1, 低电平有效
else begin Q<=D;Qn<=~D;end
end
endmodule
////////////////////////////////////////
module dff(Q,Qn,D,CLK,Set,Reset);
input D,CLK,Set,Reset;
output Q,Qn;
reg Q,Qn;
always@(posedge CLK)
begin
if(!Reset) begin Q<=0;Qn<=1;end //同步清0, 低电平有效
else if(Set) begin Q<=1;Qn<=0;end //同步置1, 低电平有效
else begin Q<=D;Qn<=~D;end
end
endmodule
/////////////////////////////////////////////////////////////////////
同步清零：
//功能文件
module dff_tongbu(D,CLK,CLR,Q);
input D,CLK,CLR;
output Q;
reg Q;
always@(negedge CLK)
if(!CLR) Q=0;
else Q=D;
endmodule
//测试文件
`timescale 1ns/100ps
module test_dff_tongbu;
reg D,CLK,CLR;
wire Q;
initial
begin
D=0;
CLK=0;
CLR=0;
#30 CLR=1;
#15 D=1;
#10 D=0;
#20 D=1;
#10000 $finish;
end
always #10 CLK=~CLK;
dff_tongbu dff(D,CLK,CLR,Q);
endmodule
异步清零：
//功能文件
module dff_yibu(D,CLK,CLR,Q);
input D,CLK,CLR;
output Q;
reg Q;
always@(negedge CLK or negedge CLR)
if(!CLR)
D=0;
else
Q=D;
endmodule
//测试文件
`timescale 1ns/100ps
module test_dff_yibu;
reg D,CLK,CLR;
wire Q;
initial
begin
CLR=0;
#10 CLR=1;
CLK=0;
D=0;
#20 D=0;
#25 D=1;
#10000 $finish;
end
always #10 CLK=~CLK;
dff_yibu dff(D,CLK,CLR,Q);
endmodule
/////////////////////////////////////////
//十进制计数器
module cnt_10(CLK,Q_out);
input CLK;
output[3:0]Q_out;
reg[3:0]Q_out;
always@(posedge CLK)
begin
if(Q_out==9) Q_out<=0;
else Q_out<=Q_out+1'b1;
end
endmodule
/////////////////////////////////////////////
//可加可减的计数器
module updown_count(D,CLK,Clear,Load,up_dowm,Q_out);
input[3:0]D;
input CLK,Clear,Load,up_down;
output[3:0]Q_out;
reg[3:0]cnt;
always@(posedge CLK)
begin
if(!Clear) cnt<=8'h00; //同步清零 低电平有效
else if(Load) cnt<=d; //同步预置
else if(up_down) cnt<=cnt+1'b1; //加计数器
else cnt<=cnt-1'b1; //减计数器
end
assign Q_out=cnt;
endmodule
///////////////////////////////////////////////////
//两位十进制计数器
module cnt_99(CLK,QH,QL);
input CLK;
output[3:0]QH,QL;
reg m;
reg[3:0]QH,QL;
always@(posedge CLK)
begin
if(QL==4'd9)
begin
QL<=4'd0;
m<=1'b1;
end
else
begin
QL<=QL+1'b1;
m<=0;
end
end
always@(posedge CLK)
begin
if(m)
if(QH==4'd9)
QH<=0;
else QH<=QH+1'b1;
end
endmodule
/////////////////////////////////////////
//带有同步复位，同步置数的模60 的计数器
moudle count60(qout,count,data,load,cin,reset,clk);
input[7:0]data;
input clk,load,cin,reset;
output count;
output[7:0]qout;
reg[7:0]qout;
always@(posedge clk)
begin
if(reset) qout<=0; //同步复位 高电平有效
else if(load) qout<=data;
else if(cin)
begin
if(qout[3:0]==9) //判断低位是否为9，是则清零
begin
qout[3:0]<=4'd0;
if(qout[7:4]==5) //判断高位是否为5，是则清零
qout[7:4]<=4'd0;
else qout[7:4]<=qout[7:4]+1'b1;
end
else qout[3:0]<=qout[3:0]+1'b1;
end
end
assign count=((qout==8'h59)&cin)?1:0;
endmodule
