中电网在线座谈技术问答

1. 进行FPGA设计，经常需要向其它芯片提供时钟，这时将涉及提供时钟反馈的问题,具体有没有高一点的好方法？

During FPGA design, both the PLD itself and other device need clock signal from outside. Our FPGA has PLL which can receive clock and output it, which has several feedback circuit. These circuit will help you to adjust the phase and frequency. You can also get the clock from clock chip directly and don"t need to go through the FPGA as you like.

2. 请介绍FPGA和CPLD的适用范围和入门开发工具。

fpga/cpld 的应用范围比较广,只要是数字信号出现的地方都可能发挥他们的作用.可以覆盖通信,医疗电子,消费类......运用可编程器件可以灵活的方便我们的设计,同时可以大幅度提高系统设计的性能.采用ALTERA MAX3000A(CPLD)和Cyclone(FPGA)同时可以获得低成本的解决方案.开发工具有Maxplus(容易上手) 和Quartus(功能强大).

3. 贵公司的EPF10K30E手册上说，可以用它来构造双端口RAM但，我在实际的使用时发现，它并不能支持标准的端口，用它构建的双断口延时长达3个时钟周期，请问我应该怎么用它来构建标准的双端口RAM。 谢谢！

EPF10K30E的EAB(专门的存储单元)能支持简单的双端口的RAM(分开的读写地址和读写使能控制),如要实现真双端口的RAM,它会用多个EAB组合实现.
CYCLONE器件具有我们最先进的RAM功能,能很好的支持真双端口功能.

4.FPGA设计低电压集成电路时应注意什么？

There are quite a few things to be considered when doing an FPGA design. For example, physically, you should consider the the i/o standards(lvttl, lvds, lvcmos, etc), core voltgae of your board. Logically, you should consider what fmax your design should be, how many resources you would use (e.g. Logic Elements, RAM blocks, I/O"s), how many clock domains you would have and how you should design your clock scheme, etc. In the perspective of design guidelines, you should avoid asynchronous paths in FPGA design; well name your design modules according to their functionaly as well as their clock scheme. This is very helpful in the design optimization stage, since you can easily find the nodes and add logic assignments. One key thing is FPGA design is you should be familiar with timing calculations, e.g. Fmax, Tsu, Tco, Thold. You should also be aware that timing is both affected by logic levels and place&route. These are only some of the considerations for your reference. There are much more that cannot simply be answered here.

5. 请问对于Cyclone系列来说，供电有什么特殊的要求 VCCIIO、VCCINT有上电顺序要求吗？

The answer is No. All Altera FPGA"s, including Cyclone, are hot-socketable,which means you can plug and unplug device while the power is ON, without damaging the device, and there"s no requirement on the order power-up for VCCIO and VCCINT.

6. 什么是Cyclone 器件系列？

Altera's new Cyclone device family is the world's lowest-cost FPGA. Designed to make the benefits of programmable logic more accessible to a broader market, Altera developed Cyclone devices specifically for high-volume applications that previously were driven by cost pressures to standard products or ASICs. The Cyclone device family has the perfect mix of features, density, and performance at less than $1.50 per 1,000 logic elements (LEs)-half the cost of competing FPGAs. Finally, system designers building high-volume applications in the consumer, communications, computer peripheral, industrial, and automotive markets now have access to the flexibility, economic efficiencies, and time-to-market advantages of programmable logic. With densities ranging from 2,910 to 20,060 logic elements (LEs), Cyclone devices are optimized for maximum logic capacity at the lowest cost. Cyclone devices feature up to 288-Kbits of embedded memory, phase-locked loops (PLLs), and support for external memory interfaces and differe

7. 设计Cyclone器件系列有什么准则?

Altera included hundreds of customers from different market segments in the product definition process to identify price threshold, features, and performance required to address high-volume applications. In addition, Altera used a ground-up approach to design the Cyclone device family, using the same methodology that was used to define the Stratix? device family. The result is Cyclone: the lowest cost FPGA ever with right mix of device capabilities.

8. 请问：如何在调试中察看EAB（例如用做FIFO或RAM时）中的大量数据，什么软件能做到这一点？

You can view the data in EAB by using SignalTapII, which is an embedded Logic Analyzer. Our software QuartusII could automatically add SignalTapII circuit into the device and output interal data to the QuartusII GUI for easy debugging

9.为什么说，Cyclone器件系列很适合代替ASIC？

Cyclone devices enable the development of new, programmable solutions in volume-driven applications where FPGAs were once considered too expensive. ASICs have high non-recurring engineering (NRE) costs, expensive design tools, and significant overall risk in bringing products to market in a timely manner. The historical price gap between a FPGA and an ASIC meant that a customer could recover the ASIC NRE charges at volumes near 10,000 units. The crossover point is anywhere from 100,000 units to 5 million units. Now system designers have access to the benefits of programmable logic-at ASIC prices.

10.在选择和DSP搭配使用时，什么时候用CPLD，什么时候用FPGA比较合适？

For low density DSP processor control signals distribution, address decoding, use CPLD. For complex DSP processor interfacing with external ASSP, use FPGA. Or if you need to implement DSP coprocessing function, FPGA is more suitable as it can implement more DSP related fucntions such as mulitplier, accumulator, shift-register, etc.

11.在quartus中,是否可以在一个project总同时使用EDF(比如说产生Nios模块)和VQM(一个顶层模块,包括其他的一些功能模块)两种方式,如果可以的化,那在compile 设置是怎样制定其工具呢(edf和vqm是由不同的第三方工具产生的).

Actually, the compiler setting is for top level module. For lower level modules, Quartus can automatically detect the synthesis tools. If you open edf and vqm file, you can find synthesis tool"s information (such as synplify and leonardo spectrum), Quartus can automatically read this information and compile the netlist appropriately.

12.在用到Cyclone器件时，遇到这样一个问题，在register-to-regiser Fmax中，如果两个寄存器的时钟是由同一个时钟不同分频得到的，他就会提示clock skew>data delay,怎么样解决这个问题

再多时钟设计中,要在软件中做相应设置.在你的设计中,你首先要设置base clock(分频前的时钟)和derived clock(分频后).具体设置见:assignmeng->timing settings->clock.对于一个绝对时钟,quartus会在timing analysis 中报告他的Fmax,但两个不同时钟源的register 之间有path,在timing analysis 中就会报告skew,而没有Fmax.关于skew的意义,你可以从2rd register 的tsu 和th 参数入手.

13.对多通道多任务的信息，处理器的处理能力及相应的缓冲存储器是很重要的，Nios 嵌入处理器在这方面的能力如何？

Nios has provided customer instruction for customer to balance performance between hardware and software. It can implement some comlicated function with hardware to accelerate the performance. And Nios provide many register and buffer for you. we have already provided the example in our web for your evaluating.

14.对MAX7000系列与ACEX系列，ACEX系列要用EPC，在可编程接线JTAG上有什么不同

Since JTAG is a standard, therefore, there are not much differences. Regarding EPC, since MAX is built by EEPROM technology, and ACEX is built by SRAM technology. MAX will not lose its contents after power down, but ACEX will lose its contents after power down. EPC is a flash-like device to store the contents for ACEX during power-down and EPC will configure the ACEX after power-up.

15.请问：Nios软嵌入RISC处理器在功能和开发上与一般的RISC处理器相比有那些优势，真的能吸引开发人员转向它吗？

NIOS has the following advantages compare to standalone processor: 1. NIOS is a soft core, can be ported to future FPGA architectures and will not stop production (other standalone will stop production). 2. NIOS provides wide variety of periphrals and customer can pick and choose different combinations and types of peripherals they really needed. e.g. 1 customer wants 20 UARTs, 1 MAC and a SDRAM controller, standalone processor cannot provide this. NIOS is much more FLEXIBLE. 3. NIOS can use FPGA logics for hardware acceleration. i.e. user can built hardware acceleration with FPGA core logics and these logics can be called by the NIOS processor as a "Custom Instruction", hence dramatically increase the overal system performance. 4. System designer don"t need to worry about software / hardware partition early in the cycle. During the middle of the design cycle, if system designer discovered that the software / hardware combination cannot meet performance, they can re-arrange some proessing using FPGA hardware easily (such as using NIOS "Custom Instruction" hardware acceleration). Or if a system designer discovered that that the software / hardware combination is an overkill of the current requirement, they can lower cost system cost by assigning some hardware processing using software instead. In summary, NIOS has much more flexibility than standalone processor. Regarding the development with NIOS, in terms of software, it is much the same as standalone processor. In terms of its hardware architecture, Altera provide an easy to use SOPC builder where customer can pick and choose different options in an easy-to-use interface and the SOPC builder will generate the NIOS hardware in the FPGA for you.

16.在编译的过程中，经常出现我所定制的管脚与编译的结果不一样请问怎样避免？

You may need to notice the pin you assigned has the IO standard support which you want to use. The software should have the same result as you assignment.

17.我有一个要求200M实时采样系统设计，希望用FPGA或CPLD作高速存储管理和简单的数据过滤计算，通过仿真发现FPGA的速度有一定的问题，没有CPLD的仿真结果理想，希望能够提一些设计和选型方面的指点，还有仿真系统和仿真软件的选择。

Our latest and greatest FPGA"s are Stratix and Cyclone. They all have different speed grades, C5, C6 and C7 for Stratix, and C6, C7 and C8 for Cyclone. Lower number means a faster device. Please try compile your design with these two devices to see if your fmax can be met. To achieve the best result, a key guideline, is you should specify all your timing requirments in QuartusII. The timing requirements should be precise and specific. For example if you have 2 clock domains, one at 100Mhz, the other 200Mhz, then you should make tell QuartusII which clock is running @100Mhz, and which is @200Mhz. Avoid just specify 200Mhz for both clocks. Also, it"s the same for i/o timings, e.g. tsu and tco. If you don"t have i/o timing requirement, then don"t specify any, if you have i/o timing requirement, then specify specifically. You could also use LogicLock feature in QuartusII to bundle critical paths or critical module together so that their delay would be minimized. Please refer to this document for further details: http://www.altera.com/literature/an/an297.pdf
For simulation software, I can only tell you that what software we"ve seen engineers using, since they all have their strengths and weakness. Some of this softwares are: For PC, ModelSim and ActiveHDL; for UNIX, VCS, VSS, and VerilogXL. Please also check the following URL, where I believe you can find a lot useful documents. http://www.altera.com/literature/lit-qts.html

18.用户能不能,用pll进行时钟倍频?如果能,怎么用;如果,不行,我们想在fpga内部实现高频信号如300兆的怎么办?

Yes, customer can use the PLL to multiply the frequency, you can implement that funcation in QII, and the software also provide the check rule for you.

19.什么是软核处理器？它的速度有通常的处理器快吗？软件许可证费用多少？

The soft processor is different from hard core, which implement with a couple of HDL file, and can be used in any device of altera families. And the performance depends on the device families you select. The customer doesn"t need ot be charged for the core license, it"s free core.

20.Cyclone器件支持什么类型的外接存储器接口？数据速度如何？

Cyclone devices, similar to the Stratix device family, can interface with single data rate (SDR) and double data rate (DDR) SDRAM devices, as well as fast cycle memory devices (FCRAM) using a dedicated, speed-optimized interface. Cyclone devices can seamlessly access these devices at speeds up to 266 megabits per second (Mbps) using a 133-MHz clock.

21.请介绍一下CPLD和FPGA的优点和缺点。它们的应用范围有何不同？可以互相替代吗？ ？

CPLD is eeprom structure, and FPGA is sram structure. The former doesn"t need the configured device, and FPGA needs. Commanly, FPGA has more logic element than CPLD, which is used for large and complicated logic function.

22.Cyclone 器件提供什么样的系统时钟管理解决方案？

Cyclone devices provide a global clock network and phase-locked loops (PLLs) with on-and-off-chip capabilities for a complete system clock management solution.

23.使用MUXPLUS 软件。自己带的VHDL编译器和外部的第三方编译器相比有什么区别。

Both MPII and third party tools can synthesis VHDL and have good performance, the customer can use it as one like.

24.有办法对FPGA的电路进行调试吗？FPGA中的设计不像程序，可以进行调试，比如单部调试、设置断点等等。如果发现FPGA的设计不能满足要求，那么有什么好办法可以发现其中的问题呢？谢谢

You can simulate the logic function you have made, both altera software and third party tools can provide simulate function. Timing simulation can test all the question of your design, that"s to say, if your design passed the timing simulation, the logic fuction should work fine on board.

25.现在的CPLD/FPGA可以支持I2C总线技术吗？应该如何开发？

cpld/fpga 可以作为I2C 协议的一个平台或载体,因此你可以据i2c协议进行cpld/fpga .流程如下:
根据协议编写源代码(原理图或VHDL或verilog HDL)->进行功能仿真(在Altera 的MAXPLUX2 或Quartus2软件里)->编译,布局布线->时序分析,时序仿真->下载,板级验证.

26.如何针对具体的应用选择cpld还是fpga,比如单片机与图形点阵lcd的接口,包含字模和控制?

The basic difference between cpld and fpga are:
1. cpld is eeprom based, so it doesn"t loose programming file upon power-off, while fpga needs to be programmed at each power-up
2. cpld is usually small in logic density and simple features, typically used for simple control logic, power management or i/o expansion. Fpga can reach very high logic density, and supple advanced features such as pll, rams, dsp, advanced i/o"s such as differential and referenced-voltaged i/o"s, so they can carry heavy and complicated logic designs.

27.能否在MAXPLUSII里调用MODELSIM进行时序仿真？怎么进行呢？

MAXPLUSII cannot call modelsim automatically, this is something that Quartus II can do. However, you can ask MAXPLUS II to generate a netlist for Modelsim simulation. Please turn on the Netlist-Writer in MAXPLUS II for netlist generation.

28.在设计中,为了少用芯片,有时不得已要在一个芯片中用到多时钟,或行波时钟,这将带来系统的不稳定,请问有无好办法解决?

the most popular FPGA like Cycone have adequate clok resorce to meet you demand.it has up to 8 global colk and 4 dedicate clock input plus some dual purpose clock input in.So,in muti-clock design,Cyclone can help improve the stability of your design.

29.CPLD中是否所有触发器的时钟输入都必须使全局时钟信号？一般综合的电路可以占用到总容量的百分之多少？

Not necessarily, normal logics can drive DFF in the CPLD, however, user has to be carefully with the extra clock skew induced by normal logics routing. Global clock is still the best to ensure minimum amount of clock skew. Recent survey from customer (we have > 14000 customer worldwide) is that most circuities can occupy over 90% of the chip"s resouces. This is mainly due to the constant improvement of our software routing algorithm in our Quartus II software.

30.如何实现FPGA的双向口？内部是否有可以直接使用的双向口？

each io of ALTERA FPGA have internal bidirectional buffer.However,you need to configure it in your souce design correctly.or you can directly call ALTERA lpm.

31.能否介绍一下HardCopy？如何实现？成本和Cyclone相比如何?

HardCopy is the convertion of FPGA to ASIC chip, unused routings in the FPGA are taken out to reduce the chip die size, hence lower the chip cost. Altera will handle the whole convertion process. Customer just need to finish the design of the selected FPGA that support HardCopy and give Altera the netlist for the conversion. For more info: http://www.altera.com/products/devices/hardcopy/hrd-index.html HardCopy is more for high-density FPGA such as Stratix. Cyclone is already at the price point and density level that can directly compete with wide range of ASIC density hence no HardCopy is needed for Cyclone. In summary, HardCopy addresses high-density, middle-to-high volumn applications, whereas, Cyclone addresses middle-to-low density, high volumn applications.