数字IC前端EDA工具使用（synopsys为主）
俗话说“磨刀不误砍柴工”，配置便捷高效的工作环境可以让数字IC设计事半功倍，目前主流的数字IC前端设计工具主要包括GVIM，Spyglass，Verdi，VCS，DC，PT,FT等工具，这些工具一般市面上的EDA虚拟机环境都有提供，这里推荐一个本人认为对新手非常友好的开源虚拟机：
https://blog.csdn.net/weixin_40377195/category_11831057.html
配置好虚拟机后，就可以开始学习各个EDA工具的使用方法啦。
1 GVIM
年少不知GVIM好，错把VScode当成宝。VScode作为一款在工科生中广泛使用的编辑器，相信许多入门IC的同学和我一样一开始会选择使用VScode进行RTL设计，VScode丰富的插件功能也很容易让人产生依赖。
然而在VScode中，编程难以脱离鼠标操作，且对于诸如注释，参数自动生成等更为底层的定制化差强人意。这个时候，GVIM闪亮登场。
这里推荐一个本人在用的GVIM插件：
开发者同时上传了使用说明，即装即用，方便快捷。
2 Spyglass
Spyglass不用多说，绝对是ICer绕不过的EDA工具。在前端设计中，主要用来进行lint检查，CDC检查，DFT检查，Power检查以及SDC检查。
本人目前只用过lint以及CDC功能，因此此处只做简单的入门讲解，后续会出一篇详细的使用文章（挖坑）。
无论进行哪种检查，Spyglass的使用都可以分为设置，运行分析，结果报告分析这三个阶段，这里是一篇以CDC检查为例的文章，非常详细，想上手Spyglass的同学可以参考：
3 VCS
VCS主要用于代码的编译与仿真，一般我会结合Verdi来用。使用VCS将编译好的波形文件输出到Verdi进行仿真结果分析。
主要Makefile脚本如下：
INCDIR = +incdir+$(DUT_DIR) \
+incdir+../../../tb
TEST_NAME = $(tc)
####coverage command
CM = -cm line+cond+fsm+branch+tgl
CM_TGL = -cm_tgl mda
CM_DIR = -cm_dir ../../../cov/$(TEST_NAME)
CM_NAME = -cm_name $(TEST_NAME)
CM_HIER = -cm_hier ../../../cfg/rtl_cov_hier.list
#################### compile command ###############################
comp：
vcs -Mdir=./$(TEST_NAME)_csrc \
-sverilog +v2k -full64 +vc \
+lint=TFIPC-L \
+vcs+flush+all \
-debug_access+all \
-timescale=1ns/1ps \
+define+$(DEFINE) \
+plusarg_save \
+plusarg_ignore \
-wreal res_sum \
-o ./simv \
-l ./compile.log \
-fsdb \
+optconfigfile+../../run/disable_timing_checks.list \
+neg_tchk \
-negdelay \
+warn=noSDFCOM_NCID \
+warn=noSDFCOM_UHICD \
-diag=sdf:verbose \
$(INCLDIR) \
-f ./rtl_tb_filelist.f \
$(CM) \
$(CM_TGL) \
$(CM_NAME) \
$(CM_DIR) \
$(CM_HIER)
#################### simulation command ###############################
sim：
./simv \
$(CM) \
$(CM_NAME) \
$(CM_DIR) \
$(TEST_PLUSARGS) \
-licqueue \
+vcs+flush+all \
+fsdb+glitch=0 \
+ntb_random_seed=$(SEED) \
-l ./$(TEST_NAME)_sim.log \
$(WAVE_ON)
4 Verdi
Verdi主要用于波形文件以及覆盖率查看，除此之外在模块的RTL代码编写完毕后也可以用Verdi读取代码进行简单的语法检查，当然VCS也是可以的，对于一些已有的设计，还可以通过Verdi简单查看原理图，便于理解电路架构。对于完整仿真模式，主要Makefile脚本如下：
verdi:
@cat $(DUT_FILELIST_VERDI) $(TB_FILELIST_VERDI) > $(RTL_TB_FILELIST)
@cd $(DIR_RESULT) && verdi -2001 $(INCLDIR) +sysvcs -sv -f ./rtl_tb_filelist.f \
-ssf ./$(TEST_NAME)*.fsdb \
-sswr ../../rc/$(TEST_NAME).rc -nologo&
对于设计检查模式，Makefile脚本如下：
verdi_dut:
@cat $(DUT_FILELIST_VERDI) > $(RTL_FILELIST) # 仅DUT文件列表
@cd $(DIR_RESULT) && verdi \
-2001 \ # Verilog-2001标准
+sysvcs \ # VCS兼容模式
-sv \ # SystemVerilog支持
-f ./rtl_filelist.f \ # 仅加载DUT文件
-nologo & # 后台运行
5 DC
在IC前端设计中，主要可以通过DC进行逻辑预综合，本人推荐这一系列博客：
6 PT
PT工具主要用于STA以及功耗分析，其中STA主要可分为布局前STA与布局后STA。
一般布局前STA会在预综合后进行，PT进行STA分析使用的主要脚本与DC类似，包括setup相关脚本，约束以及运行脚本。
PT进行STA的运行脚本如下：
点击查看代码
######################################################################
#
## PT script for pre-layout setup-time STA
#
######################################################################
##############SPECIFY LIBRARIES################
# SOURCE SETUP FILE
source "./synopsys_pt.setup"
# DEFINE OPTIONS
set report_default_significant_digits 6
set power_enable_analysis true
# SUPPRESS WARNING MESSAGES
suppress_message RC-004
suppress_message PTE-003
suppress_message UID-401
suppress_message ENV-003
suppress_message UITE-489
suppress_message CMD-041
#####################READ DESIGN###################
# DEFINE INPUT FILES
set dir "../rtl"
set in_verilog_filename "${dir}/${blockName}_netlist.v"
set in_sdc_filename "${dir}/${blockName}_sdc.sdc"
# READ
read_verilog $in_verilog_filename
read_sdc $in_sdc_filename
#read the former result
#read db
#just for multi vth
#set_user_attribute [find library CORE65LPLVT] default_threshold_voltage_group LVT
#set_user_attribute [find library CORE65LPHVT] default_threshold_voltage_group HVT
update_timing -full
#Assuming a Tcl variable TESTMODE has been defined.
#This variable is used to switch between the normal-mode and
#the test-mode for static timing analysis.Case analysis for
#normal-mode is enable when TESTMODE=1,while
#case analysis for test-mode is enable when TESTMODE =0.
#set TESTMODE [getenv TESTMODE]
#set TESTMODE 0
#if{$TESTMODE==1}{
#set_case_analysis 1 [get_port bist_mode]
#} else {
#set_case_analysis 0 [get_port bist_mode]
#}
#####################TIMING ANALYSIS#######################
# SETUP TIME
report_timing -delay_type max
# SLACK CONDITION
report_timing -delay_type min -slack_lesser_than 0.1 -max_paths 2
report_timing -delay_type max -slack_lesser_than 0.0 -max_paths 2
#The following command determines the overall health of the design
report_constraint -all_violators
####################POWER ANALYSIS#######################
report_power
###################WRITE REPORTS######################
# SET REPORT FILE NAME
set timing_rpt "${dir}/${blockName}_postsyn_timing.rpt"
set power_rpt "${dir}/${blockName}_postsyn_power.rpt"
# TIMING REPORT
report_timing > $timing_rpt
# POWER REPORT
report_power > $power_rpt
set timing_save_pin_arrival_and_slack true
########################EXIT#######################
exit
######################################################################
#
## PT script for pre-layout setup-time STA
#
######################################################################
#Define the design and read the netlist only
set active_design <design name>
read_db -netlist_only $active_design.db
current_design $active_design
set_wire_load_model <wire-load model name>
set_wire_load_model<top|enclose|segmented>
set_operating_conditions <worst-case operating condition>
#Assuming the 50pf load requirement for all outputs
set_load 50.0[all_outputs]
#Assuming the clock name is CLK with a period of 30ns
#The latency and transition are frozen to approximate the post-routed values
create_clock -period 30 -waveform [0 15] clk
create_clock_latency 3.0 [get_clocks clk]
create_clock_transition 0.2 [get_clocks clk]
set_clock_uncertainty 1.5 -setup [get_clocks clk]
#The input and output delay constraint values are assumed to be derived from the design specifications.
set_input_delay 15.0 -clock clk [all_inputs]
set_output_delay 10.0 -clock clk [all_outputs]
#Assuming a Tcl variable TESTMODE has been defined.
#This variable is used to switch between the normal-mode and
#the test-mode for static timing analysis.Case analysis for
#normal-mode is enable when TESTMODE=1,while
#case analysis for test-mode is enable when TESTMODE =0.
set TESTMODE [getenv TESTMODE]
if{$TESTMODE==1}{
set_case_analysis 1 [get_port bist_mode]
} else {
set_case_analysis 0 [get_port bist_mode]
}
#The following command determines the overall health of the design
report_constraint -all_violators
#Extensive analysis is performed using the following commands
report_timing -to [all_register -data_pins]
report_timing -to [all_outputs]
######################################################################
#
## PT script for post-layout hold-time STA
#
######################################################################
#Define the design and read the netlist only
set active_design <design name>
read_db -netlist_only $active_design.db
curren_design $active_design
set_wire_load_model <wire-load model name>
set_wire_load_model<top|enclose|segmented>
#Use best-case operating conditions for hold-time analysis
set_operating_conditions <best-case operating condition>
#Assuming the 50pf load requirement for all outputs
set_load 50.0[all_outputs]
#Back annotate the best-case(extracted)layout information
source capacitance_best.pt #actual parasitic capacitances
read_sdf rc_delays_best.sdf #actual RC delays
read_parasitics clock_info_best.spf #clock network data
#Assuming the clock name is CLK with a period of 30ns
#The latency and transition are frozen to approximate the post-routed values
create_clock -period 30 -waveform [0 15] clk
set_propagated_clock [get_clocks clk]
set_clock_uncertainty 1.5 -setup [get_clocks clk]
#The input and output delay constraint values are assumed to be derived from the design specifications.
set_input_delay 15.0 -clock clk [all_inputs]
set_output_delay 10.0 -clock clk [all_outputs]
#Assuming a Tcl variable TESTMODE has been defined.
#This variable is used to switch between the normal-mode and
#the test-mode for static timing analysis.Case analysis for
#normal-mode is enable when TESTMODE=1,while
#case analysis for test-mode is enable when TESTMODE =0.
set TESTMODE [getenv TESTMODE]
if{$TESTMODE==1}{
set_case_analysis 1 [get_port bist_mode]
} else {
set_case_analysis 0 [get_port bist_mode]
}
#The following command determines the overall health of the design
report_constraint -all_violators
#Extensive analysis is performed using the following commands
report_timing -to [all_register -data_pins] \
-delay_type min
report_timing -to [all_outputs] -delay_type min
7 FT
FT工具主要用于形式验证，实际上相对于以上的EDA工具使用较少，这里给出FT形式验证脚本：
点击查看代码
# Abstract: ${TOP} Formality Logical Equivalence Checking script
####################################################################
set start_time [clock seconds] ; echo [clock format $start_time -gmt false]
echo [pwd]
print_suppressed_messages
# Job parallelism options
####################################################################
set_host_options -max_cores 8
####################################################################
#dc set work dir
####################################################################
define_design_lib WORK -path ./work
# Set design configuration options
####################################################################
#source -echo -verbose ../scripts/configuration.tcl
# Set target technology and design configuration
####################################################################
source -echo -verbose ../../input/design.cfg
#source -echo -verbose ../scripts/technology.tcl
# Pessimistic analysis mode on constant registers
set_app_var verification_assume_reg_init none
# Identify the mode of clock gating in the design
set_app_var verification_clock_gate_hold_mode low
# Account for inversions across register boundaries
set_app_var verification_inversion_push true
# This variable should be set to the top of the Synopsys installation tree
# containing Designware
# If left blank, Designware instances are treated as black boxes
set_app_var hdlin_dwroot ""
# Example variables for investigating equivalence fails
####################################################################
# Synopsys auto setup mode changes basic settings and includes more SVF info
# * hdlin_ignore_parallel_case = false
# * verification_full_curve_signals = false
# * hdlin_ignore_set_undriven = false
# * svf_ignore_unqualified_fsm_information = false (depends on SVF)
# * verification_verify_directly_undriven_output = false
# Enable auto setup mode using:
#set_app_var synopsys_auto_setup true
# Switch off the signature analysis
#set_app_var signature_analysis_match_datapath false
#set_app_var signature_analysis_match_hierarchy false
# Increase number of failing points before halting verification (0 = unlimited)
#set_app_var verification_failing_point_limit 0
####################################################################
# Read SVF file(s) created during implementation
####################################################################
set synopsys_auto_setup true
#set svf ../${env(RUNDIR_2_SYN_OUT)}/${TOP}/${TOP}_prescan.svf
#set svf $env(RUNDIR_2_SYN_OUT)/${TOP}_prescan.svf
set svf ${FM_SVF}
#if { ![regexp {synthesis} $TOP] } {
# set_svf -append ./data/${TOP}_dft.svf
#}
# Read in the libraries to determine cell functionality
####################################################################
set_app_var search_path [concat . ${LIB_SEARCH_PATH} $search_path]
read_db ${STDCELL_LIBRARY}
read_db ${MEMORY_LIBRARY}
# Read in the reference design from RTL source ( -> r )
####################################################################
# Preferred approach is to read source RTL from verilog .vc file
# This is to check for potential inaccuracies in rtl.tcl used by synthesis
#read_verilog -r -work_library WORK -f ${RTL_FILELIST}
read_verilog -r [sh cat rtl_filelist.f]
# Alternatively, the rtl.tcl can be read directly:
#source -echo -verbose ../scripts/rtl.tcl
#read_verilog -r -work_library WORK $rtl_image
set_top r:/WORK/${TOP}
# Read in the implementation design from TOP ( -> i )
####################################################################
# Netlist file name ${TOP}.v - is passed through from fm_shell invocation
#read_verilog -i ./${env(RUNDIR_2_SYN_OUT)}/${TOP}/${TOP}_prescan.v
read_verilog -i $env(RUNDIR_2_SYN_OUT)/${TOP}_prescan.v
#set_black_box r:/WORK/GHF3016K01NA
#set_black_box r:/WORK/GHFW00064D1SA
set_top i:/WORK/${TOP}
# Configure constant ports (disable scan shift) wangshang rm 2020081719
####################################################################
#set_constant r:/WORK/${TOP}/SE_0 -type port
#set_constant i:/WORK/${TOP}/SE_0 -type port
#set_dont_verify_point i:/WORK/${TOP}/DFTSP* -type port
#set_dont_verify_point i:/WORK/${TOP}/DFTSI* -type port
# Set reference and implementation designs
####################################################################
set_reference_design r:/WORK/${TOP}
set_implementation_design i:/WORK/${TOP}
# Perform matching of compare points
####################################################################
match
report_matched_points > ./reports/${TOP}.matched_points
#report_matched_points -status unread > ./reports/${TOP}.matched_points-unread
report_unmatched_points > ./reports/${TOP}.unmatched_points
report_unmatched_points -status unread > ./reports/${TOP}.unmatched_points-unread
# Verify and report
####################################################################
set status [ verify r:/WORK/${TOP} i:/WORK/${TOP} ]
report_passing_points > ./reports/${TOP}.passing_points
report_failing_points > ./reports/${TOP}.failing_points
if { $status == 0 } {
diagnose
report_error_candidates > ./reports/${TOP}.error_candidates
save_session ./data/${TOP}.lec ;# Save session as a .fss file
} else {
echo "No candidates" > ./reports/${TOP}.error_candidates
}
# Report logical equivalence status
####################################################################
report_status
# Report message summary and quit
####################################################################
print_message_info
set end_time [clock seconds]; echo [clock format $end_time -gmt false]
#Total script wall clock run time
echo "Time elapsed: [format %02d [expr ( $end_time - $start_time ) / 86400 ]]d\
[clock format [expr ( $end_time - $start_time ) ] -format %Hh%Mm%Ss -gmt true]"
start_gui
exit
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