博客园 - YB-Park
uuid:24b78886-0ed1-41c2-8670-e3f31dcf42c4;id=22037
2014-12-01T04:47:59Z
YB-Park
https://www.cnblogs.com/capark/
feed.cnblogs.com
https://www.cnblogs.com/capark/p/4134772.html
Windows 8 64bit Xilinx ISE(14.7) Fix License - YB-Park
http://www.youtube.com/watch?v=ttPbEcNjdo8It can work successfully!
2014-12-01T04:47:00Z
2014-12-01T04:47:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】http://www.youtube.com/watch?v=ttPbEcNjdo8It can work successfully! <a href="https://www.cnblogs.com/capark/p/4134772.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/p/4121369.html
对Verilog 初学者比较有用的整理(转自它处) - YB-Park
*********************************************************************************************************************作者:Ian11122840 时间:2010-9-27 09:04...
2014-11-25T08:48:00Z
2014-11-25T08:48:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】*********************************************************************************************************************作者:Ian11122840 时间:2010-9-27 09:04... <a href="https://www.cnblogs.com/capark/p/4121369.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/p/4004478.html
Shift Register(Using Submodule) - YB-Park
/***************************************************/ Shift Register module by Submodule/ Programing by seongki***************************************...
2014-10-02T13:22:00Z
2014-10-02T13:22:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】/***************************************************/ Shift Register module by Submodule/ Programing by seongki***************************************... <a href="https://www.cnblogs.com/capark/p/4004478.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/p/4004474.html
Shift Register - YB-Park
/***************************************************/ Shift Register module/ Programing by seongki***************************************************/...
2014-10-02T13:18:00Z
2014-10-02T13:18:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】/***************************************************/ Shift Register module/ Programing by seongki***************************************************/... <a href="https://www.cnblogs.com/capark/p/4004474.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/p/4004464.html
Blocking & Nonblocking module - YB-Park
/***************************************************/ Blocking and Nonblocking circuit and Simulation/ Using level sensitive event/ Programing by seon...
2014-10-02T13:11:00Z
2014-10-02T13:11:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】/***************************************************/ Blocking and Nonblocking circuit and Simulation/ Using level sensitive event/ Programing by seon... <a href="https://www.cnblogs.com/capark/p/4004464.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/p/3992679.html
Verilog HDL test bench 문법에 관한 - YB-Park
16bit ripple carry adder test bench`timescale 1ns/1nsmodule testbench2;reg [15:0] a, [15:0] b, c_in;wire [15:0] sum, c_out;fulla16 adder(.[15:0] a([15...
2014-09-25T05:57:00Z
2014-09-25T05:57:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】16bit ripple carry adder test bench`timescale 1ns/1nsmodule testbench2;reg [15:0] a, [15:0] b, c_in;wire [15:0] sum, c_out;fulla16 adder(.[15:0] a([15... <a href="https://www.cnblogs.com/capark/p/3992679.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/p/3992669.html
ModelSim6.2 설치에 관한(About the Installation problem of ModelSim 6.2) - YB-Park
ModelSim 설치는 PC OS 따라서 호환성 문제가 발생한다.!!!!!! Vista OS에서는 ModelSim 설치가 안됨(호환성 문제)XP, Win7에서는 호환성 문제 없음!
2014-09-25T05:50:00Z
2014-09-25T05:50:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】ModelSim 설치는 PC OS 따라서 호환성 문제가 발생한다.!!!!!! Vista OS에서는 ModelSim 설치가 안됨(호환성 문제)XP, Win7에서는 호환성 문제 없음! <a href="https://www.cnblogs.com/capark/p/3992669.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/p/3992620.html
4비트,16비트 가산기에 관한 문제(계층설계) - YB-Park
Q: 수업듣는 학생의 질문1. half-addermodule half_adder (S, C, x, y);output S, C;input x, y;xor (S, x, y);and (C, x, y);endmodule2. full-addermodule full_adder (...
2014-09-25T05:30:00Z
2014-09-25T05:30:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】Q: 수업듣는 학생의 질문1. half-addermodule half_adder (S, C, x, y);output S, C;input x, y;xor (S, x, y);and (C, x, y);endmodule2. full-addermodule full_adder (... <a href="https://www.cnblogs.com/capark/p/3992620.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/archive/2012/10/31/2748740.html
有关Quartus如何自动生成 .pof 文件 - YB-Park
Quartus => Assignment=> Device=> Device and Pin Options=> Configuration=> Use configuration device(check)
2012-10-31T13:26:00Z
2012-10-31T13:26:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】Quartus => Assignment=> Device=> Device and Pin Options=> Configuration=> Use configuration device(check) <a href="https://www.cnblogs.com/capark/archive/2012/10/31/2748740.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/archive/2012/10/22/2734757.html
有关VHDL中null, 在Verilog HDL 中的表示方法 - YB-Park
VHDL: if cnt_max = maxtime then null; else @@@@@@@@@@@;Verilog: if(cnt_max == maxtime) ; else @@@@@@@@@@@@@;
2012-10-22T15:49:00Z
2012-10-22T15:49:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】VHDL: if cnt_max = maxtime then null; else @@@@@@@@@@@;Verilog: if(cnt_max == maxtime) ; else @@@@@@@@@@@@@; <a href="https://www.cnblogs.com/capark/archive/2012/10/22/2734757.html" target="_blank">阅读全文</a>
https://www.cnblogs.com/capark/archive/2012/04/02/2430282.html
第一天 - YB-Park
今天是申请博客的第一天。。。。。。。如今的互联网是如此的发达。。。 但 这是我开通的第一个博客。。。。嘿嘿。。。。2012-04-02 21:44
2012-04-02T12:46:00Z
2012-04-02T12:46:00Z
YB-Park
https://www.cnblogs.com/capark/
【摘要】今天是申请博客的第一天。。。。。。。如今的互联网是如此的发达。。。 但 这是我开通的第一个博客。。。。嘿嘿。。。。2012-04-02 21:44 <a href="https://www.cnblogs.com/capark/archive/2012/04/02/2430282.html" target="_blank">阅读全文</a>